System and method for parallel memory test

A method, comprising:

• transferring a first memory address to a first memory component and a second memory component in a first time period of a controller clock signal;
• transitioning, within the first time period of the controller clock signal, a first test-enable signal for the first memory component from a first signal value to a second signal value and transitioning a second test-enable signal for the second memory component from the second signal value to the first signal value;
• initiating, within the first time period of the controller clock signal, a first cycle of a first memory component clock signal for the first memory component based on the first test-enable signal;
• triggering, by the first cycle of the first memory component clock signal, the first memory component to read a first memory value stored at the first memory address in the first memory component;
• transitioning, at the end of the first time period of the controller clock signal, the first test-enable signal from the first signal value to the second signal value and transitioning the second test-enable signal from the second signal value to the first signal value;
• initiating, within a second time period of the controller clock signal, a first clock cycle of a second memory component clock signal for the second memory component based on the second test-enable signal transitioning from the second signal value to the first signal value;
• triggering, by the first clock cycle of the second memory component clock signal, the second memory component to read a second memory value stored at the first memory address of the second memory component;
• sending the first and second memory values from the first and second memory components, respectively, to a multiplexer;
• and
• transferring the first and second memory values serially to combining circuitry.

A device, comprising:

• a built-in self-test (BIST) controller coupled to read-only memories (ROMs);
• a memory data path circuit coupled to the BIST controller and to the ROMs;
• a control clock coupled to the memory data path circuit;
• and
• a BIST data analysis component coupled to the BIST controller, the memory data path circuit and the control clock, wherein the BIST data analysis component is configured to test memory values read from the ROMs.