Method for optimizing flash memory chip and related apparatus

A solid-state disk (SSD) controller configured to read and execute instructions and/or program code in a flash memory coupled to the SSD controller via a nonvolatile flash interface (NFI), to perform operations comprising:

• after completing write training of the NFI and establishing a data strobe signal (DQS) trigger point, determining whether a trigger condition for monitoring the NFI is met, wherein the DQS trigger point triggers the flash memory to identify an electrical level state of a write data signal (DQ) corresponding to the DQS trigger point, and the trigger condition is related to working environmental data of the NFI;
• upon determining that the trigger condition for monitoring the NFI is met, writing test data to the flash memory and performing a margin test on the NFI to determine whether the NFI passes the margin test;
• and
• upon determining that the NFI does not pass the margin test, initiating interface retraining of the NFI,
• wherein the DQS trigger point divides a cycle of the write DQ into a period before the DQS trigger point as a setup time of the write DQ and a period after the DQS trigger point as a hold time of the write DQ.

A solid-state disk (SSD), comprising an SSD controller coupled to a flash memory through a nonvolatile flash interface (NFI), wherein the SSD controller is configured to perform operations comprising:

• after completing write training of the NFI and establishing a data strobe signal (DQS) trigger point, determining whether a trigger condition for monitoring the NFI is met, wherein the DQS trigger point triggers the flash memory to identify an electrical level state of a write data signal (DQ) corresponding to the DQS trigger point, and the trigger condition is related to working environmental data of the NFI;
• upon determining that the trigger condition for monitoring the NFI is met, writing test data to the flash memory and performing a margin test on the NFI to determine whether the NFI passes the margin test;
• and
• upon determining that the NFI does not pass the margin test, initiating interface retraining of the NFI,
• wherein the DQS trigger point divides a cycle of the write DQ into a period before the DQS trigger point as a setup time of the write DQ and a period after the DQS trigger point as a hold time of the write DQ.

An electronic device comprising a solid-state disk (SSD) including an SSD controller coupled to a flash memory through a nonvolatile flash interface (NFI), wherein the SSD controller is configured to perform operations comprising:

• after completing write training of the NFI and establishing a data strobe signal (DQS) trigger point, determining whether a trigger condition for monitoring the NFI is met, wherein the DQS trigger point triggers the flash memory to identify an electrical level state of a write data signal (DQ) corresponding to the DQS trigger point, and the trigger condition is related to working environmental data of the NFI;
• upon determining that the trigger condition for monitoring the NFI is met, writing test data to the flash memory and performing a margin test on the NFI to determine whether the NFI passes the margin test;
• and
• upon determining that the NFI does not pass the margin test, initiating interface retraining of the NFI,
• wherein the DQS trigger point divides a cycle of the write DQ into a period before the DQS trigger point as a setup time of the write DQ and a period after the DQS trigger point as a hold time of the write DQ.