Data latch programming algorithm for multi-bit-per-cell memory devices

Abstract

A multi-stage method for programming an n-bit memory cell array using a fixed number of data latches is disclosed. The fixed number of data latches may be a reduced number of data latches in sense amplifier and data latch (SADL) peripheral circuitry than is required by existing programming techniques. As such, the die area taken up by the SADL circuitry can be reduced, which in turn, reduces overall chip area. The multi-stage programming method may include utilizing a first data latch to receive and store program page data and utilizing a second data latch to store bit information indicating which cells are to be targeted for the multi-stage programming. At each program stage, a respective program loop may be performed with respect to each threshold voltage distribution generated during a prior program stage to create two new threshold voltage distributions from the prior distribution.

Dependencies are inferred from the claim text.