Sense amplifier architecture providing reduced program verification time

A non-transitory computer-readable storage medium storing a plurality of instructions executable by one or more processors, the plurality of instructions when executed by the one or more processors cause the one or more processors to perform a method comprising:

• connecting a first sensing node and a second sensing node to an internal bitline of a sensing amplifier to simultaneously discharge a first capacitor connected to the first sensing node and a second capacitor connected to the second sensing node through the memory cell;
• after a first sensing period, disconnecting the second sensing node from the internal bitline, wherein the second sensing node includes a first voltage level based on discharging the second capacitor;
• after a second sensing period, disconnecting the first sensing node from the internal bitline, wherein the second sensing node include a second voltage level based on discharging the first capacitor;
• and
• latching a data state of the memory cell based on the first and second voltage levels.

A sense amplifier, the comprising:

• a first capacitor having a first plate connected to a first node and a second plate connected to a bus;
• a second capacitor having a first plate connected to a second node and a second plate connected to first voltage level;
• a first switch connected between the first and second nodes;
• a second switch connected to the first node and an internal bitline;
• at least one control circuit connected to the first and second switches, the control circuit configured to execute operations to:
• turn on the second switch to connect the first and second capacitors to the bitline to discharge the first and second capacitors through the bitline;
• turn off the first switch to disconnect the second capacitor from the bitline;
• turn off the second switch to disconnect the first capacitor from the bitline;
• latching a first sensing result to a first data latch based on a first verify voltage level and a second sensing result to a second data latch based on a second verify voltage level.