Page buffer circuit, method of operating a semiconductor memory device and semiconductor memory system
AssigneeSK hynix Inc.
InventorHyung Jin CHOI
Life of this patent
Estimating the term…
Abstract
A page buffer circuit including a data latch circuit and a sensing latch circuit. The data latch circuit configured to store data corresponding to a normal operation. The sensing latch circuit configured to receive and store the data in the data latch circuit in an entering operation in accordance with a suspend operation. The sensing latch circuit configured to transmit the data stored in the sensing latch circuit to the data latch circuit in a sensing operation in accordance with the suspend operation. The sensing latch circuit configured to suspend data in a memory cell, and to output the suspend data from the memory cell.
Claims22
A page buffer circuit comprising:
- a data latch circuit configured to store data corresponding to a normal operation;
- and
- a sensing latch circuit configured to receive and store data in the data latch circuit in an entering operation in accordance with a suspend operation, to transmit data in the sensing latch circuit to the data latch circuit in a sensing operation in accordance with the suspend operation, to sense suspend data in a memory cell, and to output the suspend data from the memory cell.
9-17. (canceled)
18-20. (canceled)
A method of operating a semiconductor memory device, the method comprising:
- performing, with the semiconductor memory device including a static type sensing latch circuit and a dynamic type data latch circuit, a normal operation;
- entering the semiconductor memory device into a suspend operation based on a command signal corresponding to the suspend operation;
- transmitting data between the data latch circuit and the sensing latch circuit;
- sensing and outputting suspend data through the sensing latch circuit;
- and
- resuming the normal operation.
A semiconductor memory system comprising:
- a semiconductor memory device including a data larch circuit and a sensing latch circuit, the data latch circuit configured to store data corresponding to a normal operation and the sensing latch circuit configured to perform a sensing operation;
- and
- a host device configured to control data transmissions between the data latch circuit and the sensing latch circuit.
Dependencies are inferred from the claim text.