Latch device, in particular for row decoding and column decoding of an eeprom memory plane

A non-volatile memory device, comprising:

• a matrix memory plane including rows and columns of non-volatile memory cells;
• and
• a row decoder including a first latch device;
• and
• a column decoder including a second latch device, the first latch device including:
• an RS type latch flip-flop configured to be supplied with a first supply voltage and a second supply voltage lower than the first supply voltage and having first and second flip-flop inputs and a flip-flop output configured to output either a high voltage or a low voltage;
• and
• a control module configured to place the latch flip-flop in a set state or in a reset state when the first supply voltage has a first value which is lower than the low voltage, to confer the high voltage on the first supply voltage and the low voltage on the second supply voltage and to simultaneously output from an output time, at the two flip-flop inputs, two input voltages corresponding to a prohibited logic state, under output conditions wherein the control module causes the latch flip-flop to output and maintain the high voltage or the low voltage on the flip-flop output in the prohibited state.

A method, comprising:

• supplying a first supply voltage to an RS type latch flip-flop of a latch device;
• supplying a second supply voltage lower than the first supply voltage to the flip-flop;
• outputting, from an output of the flip-flop, either a high voltage or a low voltage;
• having first and second flip-flop inputs and a flip-flop output configured to output either a high voltage or a low voltage;
• placing, with a control module, the flip-flop in a set state or a reset state with the first supply voltage has a first value which is lower than the
• a control module configured to place the latch flip-flop in a set state or in a reset state when the first supply voltage has a first value lower than the low voltage;
• providing the high voltage as the first supply voltage and the low voltage as the second supply voltage;
• providing, from the control module, two input voltages to two inputs of the flip-flop, the two inputs corresponding to a prohibited logic state;
• and
• causing, with the control module, the latch flip-flop to output and maintain the high voltage or the low voltage on the flip-flop output in the prohibited state.