Array dependent voltage compensation in a memory device
AssigneeSanDisk Technologies LLC
InventorsKe Zhang, Liang Li, Ming Wang
Life of this patent
Estimating the term…
Abstract
The memory device that includes a die with a CMOS wafer with programming and erasing circuitry. The die also includes a plurality of array wafers coupled with and in electrical communication with the CMOS wafer and having different programming and erasing efficiencies. Each of the array wafers includes memory blocks with memory cells. The control circuitry of the CMOS wafer is configured to output at least one of different initial programming voltages and unique erase voltages to the plurality of array wafers.
Claims20
A memory device, comprising:
- a die including a CMOS wafer that includes programming and erasing circuitry;
- a plurality of array wafers coupled with and in electrical communication with the CMOS wafer, the plurality of array wafers including memory blocks with memory cells;
- and
- the programming and erasing circuitry of the CMOS wafer being configured to output at least one of different initial programming voltages and unique erase voltages to the plurality of array wafers.
A method of operating a memory device, comprising the steps of:
- preparing a die that includes a CMOS wafer and a plurality of array wafers that are coupled with and in electrical communication with the CMOS wafer, the plurality of array wafers including memory blocks with memory cells, and the plurality of array wafers including a first array wafer and a second array wafer;
- and
- in programming operations, with programming circuitry in the CMOS wafer, applying a first initial programming voltage to the memory blocks of the first array wafer and applying a second initial programming voltage to the memory blocks of the second array wafer, the first initial programming voltage being different than the second initial programming voltage, or
- in erase operations, with erasing circuitry in the CMOS wafer, applying a first erase voltage to the memory blocks of the first array wafer and applying a second erase voltage to the memory blocks of the second array wafer, the first erase voltage being different than the second erase voltage.
An apparatus, comprising:
- a die including a CMOS wafer and a first array wafer and a second array wafer, the first and second array wafers each including at least one memory block with a plurality of memory cells, the memory cells of the first array wafer having a high programming efficiency and a high erasing efficiency, and the memory cells of the second array having a low programming efficiency and a low erasing efficiency;
- a programming and erasing means for programming and erasing the memory cells of the first and second array wafers, the programming and erasing means being configured to, in programming operations, apply a first initial programming voltage to the memory cells of the first array wafer and apply a second initial programming voltage to the memory cells of the second array wafer, the second initial programming voltage being different than the first initial programming voltage;
- and
- the programming and erasing means being further configured to, in erase operations, apply a first erase voltage to the memory cells of the first array wafer and apply a second erase voltage to the memory cells of the second array wafer, the second erase voltage being different than the first erase voltage.
Dependencies are inferred from the claim text.