Memory device and memory system including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsByunghoon JEONG, Kyungtae KANG, Jangwoo LEE, Jeongdon IHM
Life of this patent
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Abstract
A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.
Claims20
A memory controller configured to communicate with a memory device through a plurality of lines including a plurality of data lines, the memory controller comprising:
- an enable signal generator configured to generate a read enable signal and transmit the read enable signal to the memory device through one of the plurality of lines;
- and
- a first-in first-out (FIFO) circuit configured to store, in response to the read enable signal, status data received from the memory device through at least one of the plurality of data lines in a first period, and to read data received through the plurality of data lines in a second period subsequent to the first period,
- wherein the memory controller is configured to determine whether to retrain the memory device based on the status data stored in the FIFO circuit.
An operation method of a memory device, the operation method comprising:
- transmitting status data to a memory controller through at least one of a plurality of data lines in a first period, in response to a read enable signal received from the memory controller;
- and
- transmitting read data to the memory controller through the plurality of data lines in a second period subsequent to the first period.
Dependencies are inferred from the claim text.