Memory device, memory system and method for operating memory system

A memory device comprising

• a first pad configured to receive a data clock signal;
• a second pad configured to receive a command and address signal;
• a third pad configured to transmit or receive a data (DQ) signal;
• a clock distribution network configured to generate a first division clock signal for sampling the CA signal and a second division clock signal for sampling the DQ signal from the data clock signal;
• a CA sampler sampling the CA signal based on the first division clock signal;
• a DQ sampler sampling the DQ signal based on the second division clock signal;
• and
• a CA parity check circuitry triggering CA training in response to a parity error occurring for the CA signal.

A method for operating a memory system, comprising:

• transmitting a command and address (CA) signal and a data clock signal to a memory device from a memory controller, and transmitting or receiving a data signal;
• generating, by the memory device, a first division clock signal for sampling the CA signal and a second division clock signal for sampling the DQ signal from the data clock signal
• sampling, by the memory device, the CA signal based on the first division clock signal;
• outputting, by the memory device, a parity error signal in response to a parity error occurring for the CA signal;
• and
• entering, by the memory controller, CA training in response to receiving the parity error signal.