Gate driving circuit and display panel
AssigneeWuhan China Star Optoelectronics Technology Co., Ltd.
InventorsYanqing Guan, Chao Tian, Haiming Cao
Life of this patent
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Abstract
A display panel and a gate driving circuit are provided. The gate driving circuit utilizes the pull-down control module to periodically pull up and pull down the voltage level of the second node. The voltage level of the second node is periodically a high voltage level. This effectively reduces the time duration when the second node corresponds to the high voltage level. After the TFTs electrically connected to the second node are forward biased, the TFTs could have sufficient recovery time. This solution effectively improves the bias condition of the TFTs in the pull-down control module and thus makes the circuit more stable and raises the reliability of the circuit.
Claims20
A gate driving circuit, comprising a plurality of cascaded gate driving units, each of the driving units comprising:
- a pull-up control module, electrically connected to a first node, configured to control a voltage level of the first node;
- a pull-up module, electrically connected to the first node and a scan signal output end of a current stage, configured to pull up a voltage level of the scan signal output end of the gate driving unit of a current stage under a control of the voltage level of the first node;
- a pull-down module, electrically connected to the scan signal output end of the gate driving unit of the gate driving unit of the current stage, configured to pull down the voltage level of the scan signal output end of the gate driving unit of the current stage;
- and
- a pull-down control module, electrically connected to a second node, the first node, a first clock signal end and the scan signal output end of the gate driving unit of the current stage, configured to periodically pull down a voltage level of the second node under a control of an input signal of the first clock signal end to maintain the voltage level of the first node and the voltage level of the scan signal output end of the gate driving unit of the current stage.
A gate driving circuit, comprising a plurality of cascaded gate driving units, each of the driving units comprising:
- a first transistor, having a gate electrically connected to a second clock signal end, a first electrode electrically connected to a scan signal output end of a previous stage, and a second electrode electrically connected to the first node;
- a second transistor, having a gate electrically connected to the first node, a first electrode electrically connected to a third clock signal end, and a second electrode electrically connected to the scan signal output end of the gate driving unit of a current stage;
- a third transistor, having a gate electrically connected to a second clock signal end, a first electrode receiving a constant low voltage level signal, and a second electrode electrically connected to the scan signal output end of the gate driving unit of the current stage;
- a fourth transistor, having a gate electrically connected to the first clock signal end, a first electrode receiving a constant low voltage level signal, and a second electrode electrically connected to the second node;
- a fifth transistor, having a gate electrically connected to the second node, a first electrode receiving the constant low voltage level signal, and a second electrode electrically connected to the first node;
- a sixth transistor, having a gate electrically connected to the first node, a first electrode receiving the constant low voltage level signal, and a second electrode electrically connected to the second node;
- a seventh transistor, having a gate electrically connected to a fourth clock signal end, a first electrode electrically connected to the fourth clock signal end, and a second electrode electrically connected to the second node;
- and
- an eighth transistor, having a gate electrically connected to the second node, a first electrode receiving the constant low voltage level signal, and a second electrode electrically connected to the scan signal output end of the gate driving unit of the current stage.
Dependencies are inferred from the claim text.