US 2023/0401368 A1Published application

Integrated circuit device and manufacturing method of the same

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsChing-Yu HUANG, Wei-Cheng TZENG, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG

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Abstract

A method is provided, including following operations: identifying a first contact via, a second contact via, or a combination thereof in a first standard cell, wherein the first contact via is coupled between a first active region and a first conductive line on a first side, and the second contact via is coupled between a second active region and a second conductive line on a second side; calculating a first cell height according to a first width of the first and second active regions, and calculating a second cell height according to a second width of the first and second active regions; calculating multiple first available cell heights based on a ratio between the first and second cell heights; generating layout designs of multiple first cells; and manufacturing at least first one element in the integrated circuit based on the layout designs of the first cells.

Claims20

Dependent claims

A method, comprising:

identifying a first contact via, a second contact via, or a combination thereof in a first standard cell, wherein the first contact via is coupled between a first active region and a first conductive line on a first side of an integrated circuit, and the second contact via is coupled between a second active region and a second conductive line on a second side, opposite of the first side of the integrated circuit;
in response to the identification, calculating a first cell height of the first standard cell according to a first width of the first and second active regions, and calculating a second cell height of the first standard cell according to a second width, smaller than the first width, of the first and second active regions;
calculating a plurality of first available cell heights based on a ratio between the first and second cell heights of the first standard cell;
generating layout designs of a plurality of first cells that correspond to the first standard cell, wherein each of the plurality of first cells has one of the plurality of first available cell heights;
and
manufacturing at least first one element in the integrated circuit based on the layout designs of the plurality of first cells.

3 more elements

An integrated circuit, comprising:

a first cell having a first cell height, comprising:
a first pair of stacked active regions a first width;
and
a first number of first contact vias arranged on opposite sides of the first pair of stack active regions, wherein one of the first contact via couples a first active region in the first pair of stacked active regions to a first conductive line on a back side of the integrated circuit;
a second cell having a second cell height smaller than the first cell height, comprising:
a second pair of stacked active regions having a second width;
and
a second number of second contact vias, wherein one of the second contact via extends in a first direction to pass a first active region in the second pair of stacked active regions, wherein a first boundary of the second pair of stacked active regions is aligned with a first boundary of the first pair of stacked active regions in a second direction;
and
a third cell having a third cell height smaller than the first and second cell heights, comprising:
a third pair of stacked active regions having a third width,
wherein the third cell abuts one of the first and second cells.

9 more elements

A system, comprising:

a non-transitory computer readable medium for storing instructions thereon;
and
a processor connected to the non-transitory computer readable medium, wherein the processor is configured to execute the instructions for:
retrieving a standard cell from a library stored in the non-transitory computer readable medium, wherein the standard cell comprises a pair of stacked active regions;
calculating a ratio between a first cell height of the standard cell over a second cell height of the standard cell for a cell height range of the standard cell, wherein the first and second cell heights of the standard cell correspond to first and second widths of the pair of stacked active regions;
generating layout designs of a plurality of cells each corresponding to the standard cell and having a cell height in the cell height range;
and
saving the layout designs of the plurality of cells into the library stored in the non-transitory computer readable medium for signal routing.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/825,383Filed 26 May 2022
Published: 14 Dec 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification20 codes

G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
G06F 30/394
Circuit design at the physical level: routing
G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
H10D 30/0194
Forming stacked channels, e.g. changing their shapes or sizes: the stacked channels having different properties