Processor with In-Band Fault-Injection Detection in the Presence of Exceptions
AssigneeNuvoton Technology Corporation
InventorZiv Hershman
Life of this patent
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Abstract
An apparatus for protecting a processor includes an input interface and protection circuitry. The input interface is configured to monitor code instructions that are processed by the processor. One or more of the code instructions include one or more error-detection bits. The protection circuitry is configured to detect one or more errors in the program code using the error-detection bits, and to initiate responsive actions in response to detecting the errors, while accounting for exception events occurring in the processor.
Claims20
An apparatus for protecting a processor, the apparatus comprising:
- an input interface, configured to monitor code instructions that are processed by the processor, one or more of which code instructions comprising one or more error-detection bits;
- and
- protection circuitry, configured to detect one or more errors in the program code using the error-detection bits, and to initiate responsive actions in response to detecting the errors, while accounting for exception events occurring in the processor.
A processor, comprising:
- an instruction pipeline, configured to fetch and execute program code comprising code instructions, one or more of which code instructions comprising one or more error-detection bits;
- and
- protection circuitry, configured to monitor at least the error-detection bits in the code instructions, to detect one or more errors in the program code using the error-detection bits while accounting for exception events occurring in the processor, and to initiate a responsive action in response to detecting the errors.
A method for protecting a processor, the method comprising:
- monitoring code instructions that are processed by the processor, one or more of which code instructions comprising one or more error-detection bits;
- detecting one or more errors in the program code using the error-detection bits, while accounting for exception events occurring in the processor;
- and
- initiating a responsive action in response to detecting the errors.
Dependencies are inferred from the claim text.