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US 2023/0401169 A1Published application
Cryptocurrency miner and device enumeration
AssigneeChain Reaction, Ltd.
InventorsMichael Tal, Gil Shefer, Rony Gutierrez
Life of this patent
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Abstract
A cryptocurrency miner includes a serial bus, compute modules, and a controller. Each compute module includes upstream ports, downstream ports, a pass-through buffer coupling the upstream ports to the downstream ports, and a serial bus interface coupled to the serial bus via the first upstream ports and the first downstream ports. The controller controls operation of the compute modules via commands on the serial bus. The serial bus includes bus segments between respective upstream and downstream ports of the compute modules.
Claims20
A cryptocurrency miner, comprising:
- a serial bus;
- a first compute module comprising first upstream ports, first downstream ports, a first pass-through buffer coupling the first upstream ports to the first downstream ports, and a first serial bus interface coupled to the serial bus via the first upstream ports and the first downstream ports;
- a second compute module comprising second upstream ports and a second serial bus interface coupled to the serial bus via the second upstream ports;
- and
- a controller configured to control operation of the first compute module and the second compute module via commands on the serial bus;
- wherein the serial bus comprises:
- a first bus segment between the controller and the first upstream ports of the first compute module;
- and
- a second bus segment between first downstream ports of the first compute module and the second upstream ports of the second compute module;
6 more elements
A compute board, comprising:
- a compute board interface;
- a first compute module comprising first upstream ports, first downstream ports, a first pass-through buffer coupling the first upstream ports to the first downstream ports, and a first serial bus interface coupled to the first upstream ports and the first downstream ports;
- a second compute module comprising second upstream ports and a second serial bus interface coupled to the second upstream ports;
- a first bus segment between the compute board interface and the first upstream ports of the first compute module;
- and
- a second bus segment between the first downstream ports of the first compute module and the second upstream ports of the second compute module.
3 more elements
Dependencies are inferred from the claim text.