US 2023/0401161 A1 · TRANSLATION SUPPORT FOR A VIRTUAL CACHE

Abstract

Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

Claims14

Dependent claims

A method of operating a primary processor cache for a processor with virtual memory support and multiple threads, wherein a logically indexed and logically tagged cache directory is used, and wherein an entry in the directory contains an absolute memory address in addition to a corresponding logical memory address, each entry includes a valid bit for each thread that accesses each entry, comprising:

executing a lookup to determine an address for a cache line in the primary cache;
determining that the address for the cache line and an entry for the cache line are the same cache line;
in response to determining that the address and the entry are the same, setting the valid bit associated with a second thread to valid, and not invalidating the valid bit associated with other threads in the cache entry that have a valid bit in the cache entry, wherein the valid bit is independent of other valid bits in the cache entry.

Dependencies are inferred from the claim text.

Translation support for a virtual cache

Life of this patent

Translation support for a virtual cache

Life of this patent

Abstract

Claims14