Address translation prefetching for input/output devices
AssigneeMicrosoft Technology Licensing, LLC
InventorsRamakrishna HUGGAHALLI, Shachar RAINDEL
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Abstract
In one example of the present technology, an input/output memory management unit (IOMMU) of a computing device is configured to: receive a prefetch message including a virtual address from a central processing unit (CPU) core of a processor of the computing device; perform a page walk on the virtual address through a page table stored in a main memory of the computing device to obtain a prefetched translation of the virtual address to a physical address; and store the prefetched translation of the virtual address to the physical address in a translation lookaside buffer (TLB) of the IOMMU.
Claims20
An input/output memory management unit (IOMMU) of a computing device configured to:
- receive a prefetch message comprising a virtual address from a central processing unit (CPU) core of a processor of the computing device;
- perform a page walk on the virtual address through a page table stored in a main memory of the computing device to obtain a prefetched translation of the virtual address to a physical address;
- and
- store the prefetched translation of the virtual address to the physical address in a translation lookaside buffer (TLB) of the IOMMU.
An input/output device comprising:
- a controller configured to perform direct memory access (DMA) operations with a main memory of a computing device connected to the input/output device, the controller being configured to:
- receive a DMA stream setup command comprising a virtual address;
- transmit a translation request to a system memory management unit (SMMU) to receive a prefetched translation of the virtual address to a physical address;
- and
- store the prefetched translation of the virtual address to the physical address in an address translation cache of the input/output device.
A computing device comprising:
- a processor comprising:
- a central processing unit (CPU) core;
- and
- a system memory management unit (SMMU) comprising a translation lookaside buffer (TLB);
- a main memory storing a page table;
- and
- an input/output (I/O) device connected to the processor and the main memory via an interconnect,
- the CPU core being configured to:
- transmit a direct memory access (DMA) stream setup command to the I/O device, the DMA stream setup command comprising a virtual address;
- the SMMU being configured to:
- prefetch a translation of the virtual address into a physical address;
- and
- store the prefetched translation of the virtual address into the physical address in the TLB;
- the I/O device being configured to:
- receive the DMA stream setup command;
- receive the prefetched translation of the virtual address from the SMMU;
- and
- execute a DMA operation with the main memory based on the prefetched translation of the virtual address.
A non-transitory computer readable medium storing instructions that, when executed by a processor, cause the processor to prime a translation lookaside buffer (TLB) of an input/output memory management unit (IOMMU) by:
- sending, by a CPU core of the processor, a DMA stream setup command to an input/output (PO) device, the DMA stream setup command comprising a virtual address;
- and
- sending, from the CPU core of the processor, a prefetch message comprising the virtual address to the IOMMU to cause the IOMMU to:
- prefetch a translation of the virtual address into a corresponding physical address from a main memory;
- and
- store the translation of the virtual address into the corresponding physical address in the TLB of the IOMMU.
Dependencies are inferred from the claim text.