Processor and method designating an in-core cache of a hierarchical cache system to perform writing-back and invalidation of cached data

A processor, designating an in-core cache of a hierarchical cache system to perform writing-back and invalidation of cached data, comprising:

• a first core, including a decoder, a memory order buffer, and a first-level cache;
• and
• a last-level cache, coupled to the first core;
• wherein:
• the hierarchical cache system includes the first-level cache of the first core, the last-level cache, and in-core caches of the other cores of the processor, and the last-level cache is shared by the different cores of the processor;
• the decoder decodes an instruction into microinstructions, wherein the instruction is in an instruction set architecture and is executed to designate a designated-level cache within a current core as a target to perform writing-back and invalidation;
• according to the microinstructions, a level-designation request indicating the designated-level cache within the first core is transferred to the hierarchical cache system through the memory order buffer;
• and
• in response to the level-designation request, the hierarchical cache system recognizes cache lines related to the designated-level cache of the first core, writes modified cache lines, which are obtained from the recognized cache lines, back to a system memory, and then invalidates all the recognized cache lines from the hierarchical cache system.