Fpga based platform for post-silicon validation of chiplets

A method comprising:

• establishing communication with a graphics compute die (GCD) associated with a chiplet for a multi-die system on chip (SoC) device, the communication established via a field-programmable gate array (FPGA), the FPGA including hardware logic that is configurable to emulate functionality of a die of the multi-die SoC device;
• receiving signals at the FPGA via a system interconnect and, in response to the signals, driving interconnects to the GCD via general-purpose input/output (GPIO) to cause the GCD to boot into an operational state;
• and
• emulating functionality of the die of the multi-die SoC device to facilitate execution of a silicon validation test on the GCD.

A system comprising:

• a system interface;
• and
• a circuit board including:
• an active interposer coupled with the circuit board via a debug package;
• a graphics processor die coupled with the active interposer via the debug package, wherein the graphics processor die includes graphics processor resources configured to execute instructions for a multi-die system on chip (SoC) device;
• and
• a field-programmable gate array (FPGA) including hardware logic that is configurable to emulate system interface and power management circuitry of a system die of the multi-die SoC device, the FPGA to enable validation of the graphics processor die separately from the system die.