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US 2023/0401008 A1Published application
Command address input buffer bias current reduction
AssigneeLodestar Licensing Group LLC
InventorGary Howe
Life of this patent
Estimating the term…
Abstract
A memory device may include one or more memory banks that store data and one or more input buffers. The input buffers may receive command address signals to access the one or more memory banks. The memory device may operate in one of a first mode of operation or a second mode of operation. The one or more input buffers may operate under a first bias current when the memory device is in the first mode of operation or a second bias current when the memory device is in the second mode of operation, and the first bias current may be greater than the second bias current.
Claims25
A memory device comprising:
- a memory bank configured to store data;
- and
- command address circuitry configured to regulate access to the memory bank based on sets of command address signals, wherein the command address circuitry comprises a mode of operation selected from a set of modes of operation comprising a first mode of operation and a second mode of operation, wherein, in response to the mode of operation being the first mode of operation, the command address circuitry is configured to:
- read a first set of command address signals, of the sets of command address signals, during a first clock cycle;
- and
- read a second set of command address signals, of the sets of command address signals, immediately subsequent to the first set of command address signals, during a second clock cycle immediately subsequent to the first clock cycle, and
- wherein, in response to the mode of operation being the second mode of operation, the command address circuitry is configured to:
- read the first set of command address signals during the first clock cycle;
- and
- read the second set of command address signals during a third clock cycle immediately subsequent to the second clock cycle.
7 more elements
A memory device comprising:
- a memory bank configured to store data;
- and
- command address circuitry configured to regulate access to the memory bank based on sets of command address signals, wherein the command address circuitry is configured to operate in a mode of a set of modes, the set of modes comprising a 1N mode and a 2N mode, wherein, in response to operating in the 1N mode, the command address circuitry is configured to:
- read a first set of command address signals, of the sets of command address signals, during a first clock cycle;
- and
- read a second set of command address signals, of the sets of command address signals, immediately subsequent to the first set of command address signals, during a second clock cycle immediately subsequent to the first clock cycle, and
- wherein, in response to operating in the 2N mode, the command address circuitry is configured to:
- read the first set of command address signals during the first clock cycle;
- and
- read the second set of command address signals during a third clock cycle immediately subsequent to the second clock cycle.
7 more elements
A memory device comprising:
- a memory bank configured to store data;
- and
- command address circuitry configured to regulate access to the memory bank based on sets of command address signals, wherein the command address circuitry is configured to operate in a mode of a set of modes, the set of modes comprising a 1N mode and a 2N mode, wherein the memory device is configured to initialize in the 2N mode, wherein, in response to operating in the 1N mode, the command address circuitry is configured to:
- read a first set of command address signals, of the sets of command address signals, during a first clock cycle;
- and
- read a second set of command address signals, of the sets of command address signals, immediately subsequent to the first set of command address signals, during a second clock cycle immediately subsequent to the first clock cycle, and
- wherein, in response to operating in the 2N mode, the command address circuitry is configured to:
- read the first set of command address signals during the first clock cycle;
- and
- read the second set of command address signals during a third clock cycle immediately subsequent to the second clock cycle.
7 more elements
A method comprising:
- initializing a memory device in a 2N mode of a set of operating modes, the memory device comprising command address circuitry configured to regulate access to a memory bank of the memory device based on sets of command address signals, wherein the set of operating modes comprises the 2N mode and a 1N mode;
- reading, via the command address circuitry, a first set of command address signals, of the sets of command address signals, during a first clock cycle;
- and
- reading, via the command address circuitry, a second set of command address signals, of the sets of command address signals, immediately subsequent to the first set of command address signals, wherein reading the second set of command address signals comprises:
- in response to operating in the 1N mode, reading the second set of command address signals during a second clock cycle immediately subsequent to the first clock cycle;
- and
- in response to operating in the 2N mode, reading the second set of command address signals during a third clock cycle immediately subsequent to the second clock cycle.
4 more elements
Dependencies are inferred from the claim text.