Timing generator as master clock for an electronic circuit

A timing generator as master clock for an electronic circuit, wherein the timing generator is arranged and configured to generate a timestamp that comprises a coarse code and a plurality of fine codes, comprising:

• a ring oscillator with an uneven number n of delay elements, each with one delay output at which a clock signal is present, wherein each delay element is adjusted to a preset delay time;
• clock dividers, arranged at and connected to a delay output in such a manner that each delay output is connected to a clock divider, wherein the clock dividers have a clock divider output at which a clock divider output signal is output;
• a start circuit for generating an initialization signal, which is transmitted to each clock divider to trigger the clock divider, in order to place the clock divider output in a defined state and maintain it there;
• a clock generator, which is connected to a delay output and processes the clock signal further to generate the coarse code therefrom;
• and
• an output at which the generated timestamp is output;
• wherein
• the clock divider output signals from two clock dividers are shifted with respect to each other by a time difference;
• the fine codes are formed from the clock divider output signals of the clock dividers;
• the time difference of the fine codes depends on the number n and delay time of the delay elements;
• the timestamp is formed from the fine codes and the coarse code;
• the coarse code and the fine codes comprise redundant information in such a manner that a time shift of the fine codes with respect to a coarse code by a maximum of (n−1)/2 time differences results in a correct timestamp.

A method for generating a timestamp as master clock for an electronic circuit, comprising the following steps:

• generating an uneven number n of clock signals that are time delayed with respect to each other;
• supplying each clock signal to a clock divider for dividing the frequency of the clock signal and for generating one fine code for each in such a manner that two fine codes are shifted by a time difference with respect to each other;
• generating an initialization signal;
• transmitting the initialization signal to each of the clock dividers for enabling the clock dividers;
• generating a coarse code from one of the clock signals;
• generating a timestamp from the coarse code and the plurality of fine codes, such that the coarse code and the fine codes have redundant information in such a manner that even a time shift of the fine codes by at most (n−1)/2 time differences with respect to a coarse code results in a correct timestamp.