Booth multiplier for compute-in-memory

A memory device, comprising compute-in-memory hardware including:

• a Booth encoder having:
• an exclusive OR gate coupled to a first data input line and a second data input line at inputs of the exclusive OR gate;
• an exclusive NOR gate coupled to the second data input line and a third data input line at inputs of the exclusive NOR gate;
• a first NOR gate coupled to an output of the exclusive OR gate and an output of the exclusive NOR gate at inputs of the first NOR gate;
• a second NOR gate coupled to the output of the exclusive OR gate and an output of the first NOR gate at inputs of the second NOR gate;
• and
• a third NOR gate coupled to an output of the second NOR gate at an input of the third NOR gate and coupled to the third data input line at an inverted input of the third NOR gate;
• and
• a Booth decoder having:
• a plurality of multiplexers coupled to weight data input lines and an output of the third NOR gate;
• and
• a plurality of adders, wherein a first adder of the plurality of adders is coupled to outputs of a subset of the plurality of multiplexers, the output of the first NOR gate, the output of the second NOR gate, and the output of the third NOR gate.