Method of interleaved processing on a general-purpose computing core

A programmable data processing apparatus (70) comprising:

• a combined data processing and storage unit (72) comprising at least one arithmetic logic unit (41) capable of executing data-transforming operations specified by an instruction set architecture of the apparatus (70), such as arithmetic, logic, or other foundational data-transforming operations on data of all data types supported by the apparatus (70) as per the instruction set architecture of the apparatus (70), and at least one memory system (42) for storing the data and code pertaining to said operations, and
• a programmable control unit (71) for executing further, for example, control-related operations specified by the instruction set architecture other than the data-transforming operations, such as pointer dereferencing, data fetch, data store, comparison, instruction fetch, decode, dispatch or branch,
• the control unit (71) being adapted to, under control by code fetched from the processing and storage unit (72) by data transport means (76), obtain operand data from the processing and storage unit (72) by operand data transport means (77, 78), and to control the processing and storage unit (72), by a set of mutually independent parallel instruction transport means (75), using transaction control words specifying the data-transforming operations to be performed, the operand data to be processed by said data-transforming operations, and destination locations or addresses for results of said data-transforming operations,
• characterized in that
• the apparatus (70) is configured to, in at least one operational mode, write the results of the data-transforming operations directly to a destination address within the memory system (42) and
• any setup of the processing and storage unit (72) with a set (73) of mutually independent arithmetic logic units (41) for executing the data-transforming operations in parallel, with a set (74) of mutually independent memory systems (42) for storing the results of said parallel data-transforming operations in parallel, and with a set (79) of mutually independent parallel data transport means (47) for directly transferring the results of said parallel data-transforming operations from the set (73) of mutually independent arithmetic logic units (41) to the set (74) of mutually independent memory systems (42) in the at least one operational mode of the apparatus (70) is adapted to execute at least one very long transaction word comprising a set of parallel transactions issued by the control unit (71) via the set of instruction transport means (75) to the set (73) of mutually independent arithmetic logic units (41) of the processing and storage unit (72), said transaction word comprising at least one transaction which differs from at least one second transaction within the same transaction word with respect to its instruction type.