Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix Multipliers
AssigneeIntel Corporation
InventorsJack Z. Yinger, Andrew Ling, Tomasz Czajkowski, Davor Capalija, Eriko Nurvitadhi, Deborah Marr
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Abstract
Matrix multiplication systolic array feed methods and related processing element (PE) microarchitectures for efficiently implementing systolic array generic matrix multiplier (SGEMM) in integrated circuits is provided. A systolic array architecture may include a processing element array, a column feeder array, and a row feeder array. A bandwidth of external memory may be reduced by a factor of reduction based on interleaving of the matrix data via a feeding pattern of the column feeder array and the row feeder array.
Claims21
(canceled)
Circuitry of an integrated circuit, comprising:
- a plurality of processing elements comprising respective dot product circuitry and accumulator circuitry;
- loading circuitry to retrieve a first block of a first matrix and a first block of a second matrix from a memory;
- and
- feeder circuitry comprising a plurality of banks to store respective segments of the first block of the first matrix and respective segments of the first block of the second matrix and to feed the respective segments of the first block of the first matrix and the respective segments of the first block of the second matrix to the plurality of processing elements interleaved over time.
A method comprising:
- loading a first block of a first matrix and a first block of a second matrix from memory into feeder circuitry;
- feeding different segments of the first block of the first matrix and the first block of the second matrix at different times from the feeder circuitry into a plurality of processing elements;
- and
- obtaining a matrix multiplication product of the first block of the first matrix and the first block of the second matrix by accumulating matrix multiplications of the different segments of the first block of the first matrix and the first block of the second matrix at the different times using the plurality of processing elements.
An article of manufacture comprising tangible, non-transitory, machine-readable media comprising instructions to implement the following circuitry on a programmable logic device:
- a plurality of processing elements comprising respective dot product circuitry and accumulator circuitry;
- loading circuitry to retrieve a first block of a first matrix and a first block of a second matrix from a memory;
- and
- feeder circuitry comprising a plurality of banks to store respective segments of the first block of the first matrix and respective segments of the first block of the second matrix and to feed the respective segments of the first block of the first matrix and the respective segments of the first block of the second matrix to the plurality of processing elements interleaved over time.
Dependencies are inferred from the claim text.