Enhanced mosfet with superior rf performance

A method of fabricating a transistor, the method comprising:

• forming a first dielectric layer on an implant layer,
• forming a source contact, a drain contact, and a gate structure within the first dielectric layer, the gate structure being between the source contact and the drain contact and comprising a gate oxide, a gate on the gate oxide, a source side spacer on sides of the gate and the gate oxide facing the source contact, and a drain side spacer on sides of the gate and the gate oxide facing the drain contact;
• forming a source implant structure within the implant layer and electrically coupled with the source contact, the source implant structure comprising a source well below the source contact, a source extension extending from the source well to below at least a portion of the source side spacer, and a source halo below the source extension and vertically overlapping at least a part of the source side spacer;
• and
• forming a drain implant structure within the implant layer and electrically coupled with the drain contact, the drain implant structure comprising a drain well below the drain contact, a drain extension extending from the drain well to below at least a portion of the drain side spacer, and a drain halo below the drain extension and vertically overlapping at least a part of the drain side spacer,
• wherein the transistor has an asymmetric resistance or an asymmetric capacitive coupling or both, the asymmetric resistance being when a resistance of the drain implant structure is different from a resistance of the source implant structure, and the asymmetric capacitive coupling being when a capacitive coupling between the gate and the source contact is different from a capacitive coupling between the gate and the drain contact.

An amplifier comprising:

• an amplifying transistor, a source of the amplifying transistor being configured to receive a low voltage, and a gate of the amplifying transistor being configured to receive an input voltage;
• and
• a cascode transistor, a source of the cascode transistor being configured to connect with a drain of the amplifying transistor, a gate of the cascode transistor being configured to receive a bias voltage, and a drain of the cascode transistor being configured to output an amplified version of the input voltage,
• wherein the cascode transistor has an asymmetric resistance or an asymmetric capacitive coupling or both, the asymmetric resistance of a transistor being when a resistance of a drain of the transistor is different from a resistance of a source of the transistor, and the asymmetric capacitive coupling of a transistor being when a capacitive coupling between a gate and a source of the transistor is different from a capacitive coupling between the gate and a drain of the transistor.