Defect Reduction Through Scheme Of Conductive Pad Layer And Capping Layer

A device, comprising:

• an interconnect structure that includes at least a first interconnect element and a second interconnect element;
• an etch stop layer formed over the interconnect structure;
• a passivation layer formed over the etch stop layer;
• a diffusion barrier layer, wherein a first segment of the diffusion barrier layer at least partially extends through the etch stop layer and is electrically coupled to the first interconnect element, and wherein a second segment of the diffusion barrier layer is formed over the passivation layer;
• a conductive pad layer formed over the diffusion barrier layer, wherein the conductive pad layer includes aluminum that is doped with silicon or aluminum that is doped with ruthenium;
• a capping layer formed over the conductive pad layer;
• a dielectric layer formed over the capping layer;
• a conductive contact that extends vertically through at least a first portion of the dielectric layer and the capping layer, wherein the conductive contact is electrically coupled to the conductive pad layer;
• a conductive via that extends vertically through at least a second portion of the dielectric layer, the passivation layer, and the etch stop layer, wherein the conductive via is electrically coupled to the second interconnect element;
• and
• a pixel formed over, and electrically coupled to, the conductive via.

A method, comprising:

• forming a conductive pad layer over an interconnect structure that includes a first interconnect element and a second interconnect element, wherein the conductive pad layer has a first material composition;
• forming a capping layer over the conductive pad layer, wherein the capping layer has a second material composition;
• performing a patterning process, the patterning process removing portions of the conductive pad layer and the capping layer over the second interconnect element;
• forming a dielectric layer over the capping layer;
• etching a contact hole and a via hole through the dielectric layer, wherein the contact hole partially exposes the first interconnect element, and wherein the via hole partially exposes the second interconnect element;
• and
• filling the contact hole with a conductive contact and filling the via hole with a conductive via;
• wherein the forming the conductive pad layer and the forming the capping layer are performed such that:
• the first material composition include aluminum that is doped with copper, and the second material composition includes titanium nitride;
• or
• the first material composition include aluminum that is doped with silicon or ruthenium, and the second material composition includes silicon oxynitride;
• or
• the first material composition include aluminum that is doped with silicon or ruthenium, and the second material composition includes titanium nitride.