Amplifier with low-gain architecture for mmwave radio frequency (rf) signals

A method of wireless communication, the method comprising:

• determining a radio frequency (RF) amplifier gain setting;
• and
• configuring a radio frequency (RF) amplifier based on the radio frequency (RF) amplifier gain setting by performing operations of:
• controlling a configurable first stage bypass of a first stage amplifier of the radio frequency (RF) amplifier;
• and
• controlling a configurable second stage bypass of a second stage amplifier of the radio frequency (RF) amplifier.

An apparatus, comprising:

• a wireless radio, the wireless radio comprising a radio frequency (RF) amplifier, the RF amplifier comprising:
• a first stage amplifier;
• a second stage amplifier;
• a configurable first stage bypass coupled between a first input and a first output of the first stage amplifier;
• and
• a configurable second stage bypass coupled between a second input and a second output of the second stage amplifier;
• at least one processor coupled to the wireless radio;
• and
• a memory coupled to the at least one processor,
• wherein the at least one processor is configured to perform operations comprising:
• determining a RF amplifier gain setting;
• and
• configuring the RF amplifier based on the RF amplifier gain setting by performing operations of:
• controlling the configurable first stage bypass of the RF amplifier;
• and
• controlling the configurable second stage bypass of the RF amplifier.

An apparatus, comprising:

• a radio frequency (RF) low noise amplifier (LNA) comprising an amplifier input and an amplifier output, comprising:
• a first gain transistor comprising a first input and a first output, wherein the first input is coupled to the amplifier input;
• a first bypass transistor comprising a second input and a second output, wherein the second input is coupled to the amplifier input and the second output is coupled to the first output;
• a second gain transistor comprising a third input and a third output, wherein the third input is coupled to the second output and the third output is coupled to the amplifier output;
• and
• a second bypass transistor comprising a fourth input and a fourth output, wherein the fourth input is coupled to the third input and the fourth output is coupled to the amplifier output.