Memory devices having special mode access
AssigneeMicron Technology, Inc.
InventorsTheodore T. Pekny, Victor Y. Tsai
Life of this patent
Estimating the term…
Abstract
Memory devices are provided that include special operating modes accessible upon receipt of a particular message from a host. One device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.
Claims20
A NAND flash memory device comprising:
- a controller;
- a memory buffer;
- and
- a NAND memory array comprising a one time programmable (OTP) block comprising a plurality of OTP pages, wherein each of the plurality of OTP pages is associated with a flash lock enable bit configured to disallow writing to each of the plurality of OTP pages when the flash lock enable bit is set.
A memory device comprising:
- a memory array comprising a one time programmable (OTP) portion;
- and
- a serial controller configured to receive a first serial message from a host, wherein the serial message is configured to cause the memory device to permit access to the OTP portion.
A NAND flash memory device comprising:
- a controller comprising only four interface pins including a chip select pin, a clock input pin, a data input pin, and a data output pin;
- a plurality of registers in volatile memory;
- and
- a NAND memory array.
A method comprising:
- listening on a chip select input pin of a memory device for a chip select signal;
- determining whether the chip select signal transitions from high to low based on upon receiving the chip select signal;
- reading a first set of bits from a data input pin of the memory device into a state machine of a serial interface controller of the memory device;
- determining whether the first set of bits is a valid command;
- and
- reading a second set of bits from the data input pin if the first set of bits is determined to be a valid command, wherein the second set of bits immediately follows the first set of bits.
Dependencies are inferred from the claim text.