Non-volatile memory cell

A non-volatile memory cell, comprising:

• a body;
• a first well of a first conductivity type in the body;
• a second well of a second conductivity type in the body, the first and second well being arranged adjacent and contiguous to each other, wherein the first conductivity type is N-type and the second conductivity type is P-type;
• a first conduction region, a second conduction region and a third conduction region in the first well, the first, second and third conduction regions being of the second conductivity type;
• a control gate region of the second conductivity type in the second well;
• a selection gate over the first well forming, together with the first and second conduction regions, a selection transistor;
• and
• a floating gate region having a programming portion overlying the first well and a capacitive portion overlying the second well, the floating gate region forming, together with the second and third conduction regions, a storage transistor and, together with the control gate region, a capacitive element, wherein the memory cell is configured to be programmed by the channel hot electron injection effect at the storage transistor.

A non-volatile memory array comprising:

• a bitline;
• a wordline;
• a selection line;
• a first well biasing terminal;
• a second well biasing terminal coupled to the wordline;
• and
• a non-volatile memory cell comprising:
• a body,
• a first well of a first conductivity type in the body,
• a second well of a second conductivity type in the body, the first and second well being arranged adjacent and contiguous to each other, wherein the first conductivity type is N-type and the second conductivity type is P-type,
• a first conduction region, a second conduction region and a third conduction region in the first well, wherein the first, second and third conduction regions are of the second conductivity type, the first conduction region is coupled to the first well biasing terminal, and the third conduction region is coupled to the bitline,
• a control gate region of the or second conductivity type in the second well, wherein the control gate region is coupled to the second well biasing terminal,
• a selection gate over the first well forming, together with the first and second conduction regions, a selection transistor, wherein the selection gate is coupled to the selection line, and
• a floating gate region having a programming portion overlying the first well and a capacitive portion overlying the second well, the floating gate region forming, together with the second and third conduction regions, a storage transistor and, together with the control gate region, and a capacitive element.

A method for programming a non-volatile memory cell comprising a body;

• a first well of a first conductivity type in the body;
• a second well of a second conductivity type in the body, the first and second well being arranged adjacent and contiguous to each other, wherein the first conductivity type is N-type and the second conductivity type is P-type;
• a first conduction region, a second conduction region and a third conduction region in the first well, the first, second and third conduction regions being of the second conductivity type;
• a control gate region of the second conductivity type in the second well;
• a selection gate over the first well forming, together with the first and second conduction regions, a selection transistor;
• a floating gate region having a programming portion overlying the first well and a capacitive portion overlying the second well, the floating gate region forming, together with the second and third conduction regions, a storage transistor and, together with the control gate region, and a capacitive element, the method comprising:
• turning on the selection transistor;
• bringing the storage transistor in a programming current conduction condition;
• and
• generating a programming electric field at the storage transistor.