Body bias voltage generator and semiconductor device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorYoungjae KIM
Life of this patent
Estimating the term…
Abstract
A body bias voltage generating circuit includes a current mirror circuit configured to generate and input a target current to a target semiconductor element, the target semiconductor element configured to be set to a turned-on state; and a charge pump circuit including an oscillator configured to output a clock signal based on a result of comparing an output voltage of the target semiconductor element with a reference voltage, and at least one charge pump outputting a body bias voltage to each of a plurality of semiconductor elements, wherein each of the plurality of semiconductor elements is the same as or is the same type as the target semiconductor element.
Claims20
A body bias voltage generating circuit comprising:
- a current mirror circuit configured to generate and input a target current to a target semiconductor element, the target semiconductor element being in a turned-on state;
- and
- a charge pump circuit including an oscillator configured to output a clock signal based on a result of comparing an output voltage of the target semiconductor element with a reference voltage, and at least one charge pump configured to output a body bias voltage to each of a plurality of semiconductor elements,
- wherein each of the plurality of semiconductor elements has a same conductivity type as the target semiconductor element.
A body bias voltage generating circuit comprising:
- a plurality of first semiconductor elements in a first impurity region;
- a plurality of second semiconductor elements in a second impurity region, different from the first impurity region;
- a first comparator configured to compare an output voltage of a first target semiconductor element with a reference voltage, the first target semiconductor element having a same conductivity type as the plurality of first semiconductor elements and configured to receive a first target current;
- a first charge pump circuit including a first oscillator configured to operate based on an output of the first comparator, and at least one negative charge pump configured to output a negative voltage in response to a first clock signal output by the first oscillator;
- a second comparator configured to compare an output voltage of a second target semiconductor element with the reference voltage, the second target semiconductor element having a same electrical characteristic as the plurality of second semiconductor elements and configured to receive a second target current;
- and
- a second charge pump circuit including a second oscillator configured to operate based on an output of the second comparator, and a second charge pump circuit configured to output a positive voltage in response to a second clock signal output by the second oscillator.
A semiconductor device comprising:
- a memory cell array in which a plurality of memory cells are arranged;
- and
- a peripheral circuit connected to the memory cell array through a plurality of wordlines and a plurality of bitlines and configured to control the plurality of memory cells,
- wherein the peripheral circuit includes at least one semiconductor elements and a body bias adjustment circuit adjusting a body bias voltage of at least one of the plurality of semiconductor elements, and
- the body bias adjustment circuit includes a target semiconductor element having a same conductivity type as the at least one semiconductor element, a comparator configured to compare an output voltage of the target semiconductor element with a reference voltage, and a charge pump configured to adjust a body bias voltage input to a body terminal of each of the at least one semiconductor element and the target semiconductor element based on an output of the comparator.
Dependencies are inferred from the claim text.