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US 2023/0317579 A1Published application
Semiconductor package with guide pin
AssigneeSemiconductor Components Industries, LLC
InventorsChee Hiong CHEW, Yushuang YAO, Atapol PRAJUCKAMOL, Chuncao NIU
Life of this patent
Estimating the term…
Abstract
A semiconductor guide pin is disclosed. Specific implementations may include a heatsink, one or more substrates coupled together, one or more pressfit pins coupled to the one or more substrates, and two or more guide pins coupled to the one or more substrates, where the two or more guide pins may have a height greater than the one or more pressfit pins.
Claims20
A semiconductor package, comprising:
- one or more substrates coupled together;
- one or more pressfit pins coupled to the one or more substrates;
- and
- two or more guide pins coupled on a first side of the one or more substrates;
- wherein each of the two or more guide pins comprises a stress relief portion;
- and
- wherein the two or more guide pins have a height greater than the one or more pressfit pins.
4 more elements
A semiconductor package, comprising:
- one or more substrates coupled together;
- one or more pressfit pins coupled to the one or more substrates;
- and
- two or more guide pins coupled to the one or more substrates;
- wherein each guide pin comprises a stress relief portion;
- and
- wherein the two or more guide pins are configured to align the one or more pressfit pins with corresponding openings in a printed circuit board.
4 more elements
A semiconductor guide pin, comprising:
- a first portion coupled with a stress relief portion;
- wherein the first portion is configured to couple to a printed circuit board to align a plurality of pressfit pins with a plurality of openings in the printed circuit board;
- and
- wherein the semiconductor guide pin is configured to be electrically isolated when coupled to a substrate.
1 more element
Dependencies are inferred from the claim text.