Reconfigurable cache hierarchy framework for the storage of fpga bitstreams
AssigneeNokia Solutions and Networks Oy
InventorsAndrea ENRICI, Julien LALLET
Life of this patent
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Abstract
A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.
Claims10
A multi-level cache hierarchy for storing bitstreams, the multi-level cache hierarchy comprising:
- a first cache level having a first cache to store a first set of the bitstreams, the first cache having a first access time and a first storage capacity;
- a second cache level having a second cache to store a second set of the bitstreams, the second cache having a second access time and a second storage capacity, the second access time being greater than the first access time and the second storage capacity being greater than the first storage capacity;
- and
- a third cache level having a third cache to store a third set of the bitstreams, the third cache having a third access time and a third storage capacity, the third access time being greater than the second access time and the third storage capacity being greater than the second storage capacity.
A network-based apparatus comprising:
- at least one processor;
- and
- at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the network apparatus to
- configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device, and
- dynamically update pointers for the bitstreams at runtime based on changes to dynamic characteristics of the bitstreams, a pointer for a bitstream, among the pointers for the bitstreams, being based on at least one static characteristic and at least one dynamic characteristic, among the dynamic characteristics, the at least one dynamic characteristic including a frequency of request of the bitstream, and the at least one static characteristic including at least one of FPGA model, bitstream producer or shell type for the bitstream.
Dependencies are inferred from the claim text.