Storing instructions from second storage to first storage while fetch operation is stalled, and reading instructions from first instruction storage upon resuming fetch operation

A method comprising:

• sharing a first instruction storage among a plurality of sets of fetch circuitry spanning a plurality of pipeline stages;
• sharing a second instruction storage among the plurality of sets of fetch circuitry spanning the plurality of pipeline stages;
• and
• initiating a fetch operation for a block of instructions, with a first set of fetch circuitry of the plurality of sets of fetch circuitry, the fetch operation indicating that the block of instructions is to be read from the second instruction storage;
• retaining the fetch operation at a pipeline stage of the plurality of pipeline stages of the first set of fetch circuitry, for one or more cycles, until a hazard corresponding to the pipeline stage has been removed;
• storing the block of instructions from the second instruction storage to the first instruction storage, during the one or more cycles;
• and
• once the hazard has been removed, reading the block of instructions from the first instruction storage for the fetch operation.

A computer system comprising:

• a dynamic random access memory (DRAM);
• and
• a processor coupled with the DRAM, the processor comprising:
• a first instruction storage;
• a second instruction storage;
• and
• a fetch unit coupled with the first and second instruction storage, the fetch unit including a plurality of sets of fetch circuitry, including a first set of fetch circuitry, each of the sets of fetch circuitry spanning a same plurality of pipeline stages, the first set of fetch circuitry to:
• initiate a fetch operation for a block of instructions, the fetch operation to have an indication that the block of instructions is to be read from the second instruction storage;
• retain the fetch operation for the block of instructions at a pipeline stage of the plurality of pipeline stages, for one or more cycles, until a hazard corresponding to the pipeline stage of the first set of fetch circuitry has been removed;
• store the block of instructions from the second instruction storage to the first instruction storage, during the one or more cycles;
• and
• once the hazard has been removed, read the block of instructions from the first instruction storage, for the fetch operation.