Reduced logic conversion of binary integers to binary coded decimals

A chip for reduced logic conversion of binary integers to binary coded decimals, comprising:

• generating, from an input binary integer, an intermediate value comprising all zero digits encoded in an intermediate format;
• until each bit of the input binary integer has been shifted into the intermediate value:
• shifting a bit of the input binary integer into the intermediate value;
• doubling the intermediate value;
• converting the intermediate value to a binary encoded decimal output;
• and
• wherein the intermediate format comprises, for each digit of the intermediate value, a plurality of bits corresponding to a plurality of even weights, a first bit corresponding to a one weight, and a second bit corresponding to an inverse of the one weight.

An apparatus for reduced logic conversion of binary integers to binary coded decimals, comprising:

• generating, from an input binary integer, an intermediate value comprising all zero digits encoded in an intermediate format;
• until each bit of the input binary integer has been shifted into the intermediate value:
• shifting a bit of the input binary integer into the intermediate value;
• doubling the intermediate value;
• converting the intermediate value to a binary encoded decimal output;
• and
• wherein the intermediate format comprises, for each digit of the intermediate value, a plurality of bits corresponding to a plurality of even weights, a first bit corresponding to a one weight, and a second bit corresponding to an inverse of the one weight.