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US 2023/0305847 A1Published application
Multi-indexed micro-operations cache for a processor
AssigneeNokia Solutions and Networks Oy
InventorPranjal Kumar Dutta
Life of this patent
Estimating the term…
Abstract
Various example embodiments for supporting a multi-indexed micro-operations cache (MI-UC) in a processor are presented. Various example embodiments for supporting an MI-UC in a processor may be configured to support an MI-UC in which, for a UC line of the MI-UC, multiple indexes into the UC line, for multiple sets of micro-operations (UOPs) stored in the UC line based on decoding of multiple instructions, are supported.
Claims23
1-22. (canceled)
An apparatus, comprising:
- a decode unit configured to decode a first instruction into a first set of micro-operations and a second instruction into a second set of micro-operations;
- and
- a micro-operations cache configured to:
- store, in a cache line of the micro-operations cache, the first set of micro-operations and the second set of micro-operations;
- and
- store, for the cache line of the micro-operations cache, an identifier of the first instruction and an entry for the second instruction, wherein the entry for the second instruction includes an identifier of the second instruction and an indication of a location of the second set of micro-operations in the cache line of the micro-operations cache.
3 more elements
A method, including:
- decoding, by a decode unit, a first instruction into a first set of micro-operations and a second instruction into a second set of micro-operations;
- storing, by a micro-operations cache in a cache line of the micro-operations cache, the first set of micro-operations and the second set of micro-operations;
- and
- storing, by the first micro-operations cache for the cache line of the micro-operations cache, an identifier of the first instruction and an entry for the second instruction, wherein the entry for the second instruction includes an identifier of the second instruction and an indication of a location of the second set of micro-operations in the cache line of the micro-operations cache.
1 more element
A micro-operations cache, comprising:
- a memory;
- and
- a controller configured to:
- store, in a cache line of the micro-operations cache, a first set of micro-operations based on decoding of a first instruction and a second set of micro-operations based on decoding of a second instruction;
- and
- store, for the cache line of the micro-operations cache, an identifier of the first instruction and an entry for the second instruction, wherein the entry for the second instruction includes an identifier of the second instruction and an indication of a location of the second set of micro-operations in the cache line of the micro-operations cache.
3 more elements
Dependencies are inferred from the claim text.