Memristive logic gate circuit
AssigneeTechnische UniversitäT Wien
InventorNima Taherinejad
Life of this patent
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Abstract
Memristive logic gate circuit, comprising a first memristive device (1), representing a first input node A of the logic gate circuit, a second memristive device (2), representing a second input node B of the logic gate circuit, and a third memristive device (3), representing an output node F of the logic gate circuit, wherein the first memristive device (1) and the second memristive device (2) are connected in series between a positive supply voltage terminal Vx (7) and a negative supply voltage terminal −Vx (8), wherein a connection point (6) is formed between the first memristive device (1) and the second memristive device (2), and wherein the third memristive device (3) is provided between the connection point (6) and a Ground contact (9).
Claims13
Memristive logic gate circuit, comprising a first input memristive device (1), a second input memristive device (2), and an output memristive device (3), characterized in that
- the first input memristive device (1) and the second input memristive device (2) are connected in series between a positive supply voltage terminal Vx (7) and a negative supply voltage terminal −Vx (8), wherein
- a connection point (6) is formed between the first input memristive device (1) and the second input memristive device (2), and wherein
- the output memristive device (3) is provided between the connection point (6) and a Ground contact (9).
Dependencies are inferred from the claim text.