Timing sequence generation circuit
AssigneeSTMicroelectronics (Alps) SAS
InventorThomas Jouanneau
Life of this patent
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Abstract
In accordance with an embodiment, a timing sequence generation circuit includes: a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another; a first shift register comprising a flip-flop having a clock input coupled to a clock signal input of the first shift register and an output coupled to an output of the first shift register; and a first circuit configured to: select a clock signal from among the clock signals; and deliver the selected clock signal to the clock signal input of the first shift register
Claims20
A timing sequence generation circuit comprising:
- a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another;
- a first shift register comprising a flip-flop having a clock input coupled to a clock signal input of the first shift register and an output coupled to an output of the first shift register;
- and
- a first circuit configured to:
- select a clock signal from among the clock signals;
- and
- deliver the selected clock signal to the clock signal input of the first shift register.
A method of generating a timing sequence using a circuit comprising a ring oscillator having a plurality of clock signal outputs configured to provide clock signals delayed in time with respect to one another, and a first shift register, the method comprising:
- selecting a clock signal from among the clock signals;
- and
- delivering the selected clock signal to a clock signal input of the first shift register.
A timing sequence generation circuit comprising:
- a ring oscillator comprising a plurality of clock outputs corresponding to different phases of the ring oscillator;
- a first multiplexer having inputs coupled to the plurality of clock outputs;
- a first shift register having a clock input coupled to an output out of the first multiplexer;
- and
- a second multiplexer having inputs coupled to outputs of a plurality of registers of the first shift register and an output configured to provide a first timing sequence.
Dependencies are inferred from the claim text.