# US 2023/0276367 A1 · Power management integrated circuit, power management method, mobile device and clock adjusting method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0276367 A1 - Document ID: US20230276367A1 - Status: Published application - Kind: A1 - Application number: 18/143,105 - Filed: 2023-05-04 - Published: 2023-08-31 - Earliest claimed: 2014-08-26 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: JUNGHUN HEO; YOUNGDUK KIM; JOONSEOK KIM; DONGSUK SHIN - Web page: https://patentgrep.com/patent/US20230276367A1 ## CPC - G06F 1/30: Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) - H04W 52/0287: {changing the clock frequency of a controller in the equipment} - G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision - G06F 1/32: Means for saving power - G06F 1/3212: Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level - G06F 1/324: by lowering clock frequency - G06F 1/3296: by lowering the supply or operating voltage - H04W 52/0261: {managing power supply demand, e.g. depending on battery level} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - Y02D 30/70: in wireless communication networks - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A power management approach for a mobile device includes comparing a battery provided power supply voltage to a reference voltage in order to generate an alarm signal. In response to the alarm signal the frequency of an operating clock applied to a system-on-chip is changed. ## Claims ### Claim 1 A system-on-chip (SOC) comprising: a clock divider configured to receive a source clock and to generate an operating clock by dividing the source clock, the source clock being externally provided; a central processing unit (CPU) configured to receive the operating clock and to operate in response to the operating clock; and an interrupt controller configured to receive one of a first alarm signal and a second alarm signal and to send an interrupt signal to the CPU in response to receiving the second alarm signal, the first alarm signal and the second alarm signal being externally provided, wherein the clock divider is further configured to receive one of the first alarm signal and the second alarm signal, to generate the operating clock having a first frequency in response to receiving the first alarm signal, and to generate the operating clock having a second frequency in response to receiving the second alarm signal, the second frequency being less than the first frequency. ### Claim 2 (depends on 1) The SOC of claim 1, wherein the CPU is further configured to consume a first magnitude of power in response to receiving the interrupt signal, the first magnitude of power being less than a second magnitude of power consumed by the CPU without the interrupt signal. ### Claim 3 (depends on 1) The SOC of claim 1, wherein the clock divider is further configured to receive one of the first alarm signal, the second alarm signal and a third alarm signal and to generate the operating clock having a third frequency in response to receiving the third alarm signal, the third frequency being less than the second frequency. ### Claim 4 (depends on 1) The SOC of claim 1, wherein the clock divider is further configured to generate the operating clock having a third frequency after a delay from generating the operating clock having the second frequency in response to receiving the second alarm signal, the third frequency being higher than the second frequency. ### Claim 5 (depends on 1) The SOC of claim 1, wherein the clock divider is further configured to generate the operating clock having a third frequency in response to that a power supply voltage decrease, the third frequency being less than the second frequency. ### Claim 6 (depends on 1) The SOC of claim 1, wherein the clock divider is further configured to receive the first alarm signal, the second alarm signal and a power supply from an external power management integrated circuit. ### Claim 7 A system-on-chip (SOC) comprising: a clock divider configured to receive a source clock and to generate an operating clock by dividing the source clock, the source clock being externally provided; a central processing unit (CPU) configured to receive the operating clock and to operate in response to the operating clock; an interrupt controller configured to receive one of a first alarm signal and a second alarm signal and to send an interrupt signal to the CPU in response to receiving the second alarm signal, the first alarm signal and the second alarm signal being externally provided; and a control unit configured to generate a power management information indicating a level of a voltage in response to the second alarm signal, the power management information being communicated with an external device, wherein the clock divider is further configured to receive one of the first alarm signal and the second alarm signal, to generate the operating clock having a first frequency in response to receiving the first alarm signal, and to generate the operating clock having a second frequency in response to receiving the second alarm signal, the second frequency being less than the first frequency. ### Claim 8 (depends on 7) The SOC of claim 7, wherein the control unit is further configured to generate a clock division ratio information in response to the second alarm signal, the clock division ratio information being provided to the clock divider. ### Claim 9 (depends on 8) The SOC of claim 8, wherein the clock divider is further configured to receive one of the first alarm signal, the second alarm signal and a third alarm signal and to generate the operating clock having a third frequency in response to receiving the third alarm signal, the third frequency being less than the second frequency, and wherein the clock division ratio include a first clock division ratio corresponding to the second frequency and a second clock division ratio corresponding to the third frequency. ### Claim 10 (depends on 8) The SOC of claim 8, wherein the clock divider is further configured to generate the operating clock having a third frequency after a delay from generating the operating clock having the second frequency in response to receiving the second alarm signal, the third frequency being higher than the second frequency, and wherein the clock division ratio include a first clock division ratio corresponding to the second frequency and a second clock division ratio corresponding to the third frequency. ### Claim 11 (depends on 8) The SOC of claim 8, wherein the clock divider is further configured to generate the operating clock having a third frequency in response to that a power supply voltage decrease, the third frequency being less than the second frequency, and wherein the clock division ratio include a first clock division ratio corresponding to the second frequency and a second clock division ratio corresponding to the third frequency. ### Claim 12 (depends on 7) The SOC of claim 7, wherein the clock divider is further configured to receive the first alarm signal, the second alarm signal and a power supply from an external power management integrated circuit, and wherein the power management information is communicated with the external power management integrated circuit. ### Claim 13 A system-on-chip (SOC) comprising: a clock divider configured to receive a source clock, to generate a first operating clock by dividing the source clock, and to generate a second operating clock by dividing the source clock, the source clock being externally provided; a central processing unit (CPU) configured to receive the first operating clock and to operate in response to the first operating clock; a graphics processing unit (GPU) configured to receive the second operating clock and to operate in response to the second operating clock; an interrupt controller configured to receive one of a first alarm signal and a second alarm signal and to send an interrupt signal to the CPU in response to receiving the second alarm signal, the first alarm signal and the second alarm signal being externally provided, wherein the clock divider is further configured to receive one of the first alarm signal and the second alarm signal, to generate the first operating clock having a first frequency in response to receiving the first alarm signal, to generate the first operating clock having a second frequency in response to receiving the second alarm signal, to generate the second operating clock having a third frequency in response to receiving the first alarm signal, and to generate the second operating clock having a fourth frequency in response to receiving the second alarm signal, the second frequency and the fourth frequency being less than the first frequency and the third frequency respectively. ### Claim 14 (depends on 13) The SOC of claim 13, wherein the clock divider is further configured to receive one of the first alarm signal, the second alarm signal and a third alarm signal, to generate the first operating clock having a fifth frequency in response to receiving the third alarm signal, and to generate the second operating clock having a sixth frequency, the fifth frequency and the sixth frequency being less than the second frequency and the fourth frequency respectively. ### Claim 15 (depends on 13) The SOC of claim 13, wherein the clock divider is further configured to generate the first operating clock having a fifth frequency after a first delay from generating the first operating clock having the second frequency in response to receiving the second alarm signal, and to generate the second operating clock having a sixth frequency after a second delay from generating the second operating clock having the fourth frequency in response to receiving the second alarm signal, the fifth frequency and the sixth frequency being higher than the second frequency and the fourth frequency respectively. ### Claim 16 (depends on 13) The SOC of claim 13, wherein the clock divider is further configured to generate the first operating clock having a fifth frequency and to generate the second operating clock having a sixth frequency in response to that a power supply voltage decrease, the fifth frequency and the sixth frequency being less than the second frequency and the fourth frequency respectively. ### Claim 17 (depends on 13) The SOC of claim 13, further comprising: a control unit configured to generate a power management information indicating a level of a voltage in response to the second alarm signal, the power management information being communicated with an external device. ### Claim 18 (depends on 17) The SOC of claim 17, wherein the control unit is further configured to generate a clock division ratio information in response to the second alarm signal, the clock division ratio information being provided to the clock divider. ### Claim 19 (depends on 18) The SOC of claim 18, wherein the clock divider is further configured to receive one of the first alarm signal, the second alarm signal and a third alarm signal, to generate the first operating clock having a fifth frequency in response to receiving the third alarm signal, and to generate the second operating clock having a sixth frequency, the fifth frequency and the sixth frequency being less than the second frequency and the fourth frequency respectively, and wherein the clock division ratio include a first clock division ratio corresponding to the second frequency. a second clock division ratio corresponding to the fourth frequency, a third clock division ratio corresponding to the fifth frequency, and a fourth clock division ratio corresponding to the sixth frequency. ### Claim 20 (depends on 18) The SOC of claim 18, wherein the clock divider is further configured to generate the first operating clock having a fifth frequency after a first delay from generating the first operating clock having the second frequency in response to receiving the second alarm signal, and to generate the second operating clock having a sixth frequency after a second delay from generating the second operating clock having the fourth frequency in response to receiving the second alarm signal, the fifth frequency and the sixth frequency being higher than the second frequency and the fourth frequency respectively, wherein the clock division ratio include a first clock division ratio corresponding to the second frequency. a second clock division ratio corresponding to the fourth frequency, a third clock division ratio corresponding to the fifth frequency, and a fourth clock division ratio corresponding to the sixth frequency.