# US 2023/0275151 A1 · Field-effect transistor with hybrid switching mechanism

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- Number: US 2023/0275151 A1
- Document ID: US20230275151A1
- Status: Published application
- Kind: A1
- Application number: 17/680,365
- Filed: 2022-02-25
- Published: 2023-08-31
- Earliest claimed: 2022-02-25
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Abhishek A. Sharma; Anand S. Murthy; Tahir Ghani; Wilfred Gomes; Pushkar Sharad Ranade; Sagar Suthram
- Web page: https://patentgrep.com/patent/US20230275151A1

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 12/021: {of gated diodes, e.g. field-controlled diodes [FCD]}
- H10D 12/211: {Gated diodes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/13: Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Hybrid FETs and methods of forming such hybrid FETs are disclosed. An example hybrid FET includes a channel region, a first region, a second region, a third region, and two gates. A gate may wrap around a portion of the channel region. The channel region may be over a first substrate (e.g., a substrate on which the channel region is formed) but cross a second substrate. The channel region is shared by a MOSFET and a TFET. The first region and second region constitute the source and drain of the MOSFET and are doped with dopants of the same type. The first region and third region constitute the source and drain of the TFET and are doped with dopants of opposite types. The third region may be placed at the opposite side of the second substrate from the first region and the second region.

## Claims

### Claim 1

An integrated circuit (IC) device, comprising:
a first region, comprising a first semiconductor material with dopants of a first type;
a second region, comprising a second semiconductor material with dopants of the first type;
a third region, comprising a third semiconductor material with dopants of a second type, wherein the second type is different from the first type;
a channel region, comprising a fourth semiconductor material;
a first gate over a first portion of the channel region, wherein the first portion of the channel region is between the first region and the second region; and
a second gate over a second portion of the channel region, wherein the second portion of the channel region is between the first region and the third region.

### Claim 2 (depends on 1)

The IC device according to claim 1, wherein:
the first gate comprises a gate electrode, a first gate insulator, and a second gate insulator,
the first gate insulator is between the gate electrode and either the first region or the second region, and
the second gate insulator is between the gate electrode and the channel region.

### Claim 3 (depends on 1)

The IC device according to claim 1, wherein:
the second gate comprises a gate electrode, a first gate insulator, and a second gate insulator,
the first gate insulator is between the gate electrode and the first region or the third region, and
the second gate insulator is between the gate electrode and the channel region.

### Claim 4 (depends on 1)

The IC device according to claim 1, wherein an insulator is between a gate electrode of the first gate and a gate electrode of the second gate.

### Claim 5 (depends on 1)

The IC device according to claim 1, wherein the first gate is electrically coupled to the second gate.

### Claim 6 (depends on 1)

The IC device according to claim 1, further comprising a substrate, wherein the first region or the second region is at a first side of the substrate, the third region is at a second side of the substrate, and the first side opposes the second side.

### Claim 7 (depends on 6)

The IC device according to claim 6, wherein the first gate or the second gate is at the second side of the substrate.

### Claim 8 (depends on 6)

The IC device according to claim 6, wherein a portion of the channel region is in the substrate.

### Claim 9 (depends on 8)

The IC device according to claim 8, wherein a first portion of the channel region is at the first side of the substrate, and a second portion of the channel region is at the second side of the substrate.

### Claim 10 (depends on 1)

The IC device according to claim 1, wherein the first type is an n-type and the second type is a p-type.

### Claim 11

A method for forming an integrated circuit (IC) device, the method comprising:
providing a channel region, the channel region comprising a semiconductor material;
providing a first region at a first section of the channel region, the first region comprising a first semiconductor material with dopants of a first type;
providing a second region at a second section of the channel region, the second region comprising a second semiconductor material with dopants of the first type;
providing a third region at a third section of the channel region, the third region comprising a fourth semiconductor material with dopants of a second type, wherein the second type is different from the first type;
providing a first gate over a fourth section of the channel region, the first gate comprising a first gate electrode; and
providing a second gate over a fifth section of the channel region, the second gate comprising a second gate electrode,
wherein the fourth section is between the first section and the second section, and the fifth section is between the first section and the third section.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the first gate further comprises a first gate insulator that is between the first gate electrode and the first region or the second region, and the second gate further comprises a second gate insulator that is between the second gate electrode from the first region or the third region.

### Claim 13 (depends on 11)

The method according to claim 11, wherein the first gate further comprises a first gate insulator, the second gate further comprises a second gate insulator, the first gate insulator is between the fourth section and the first gate electrode, the second gate insulator is between the fifth section and the second gate electrode.

### Claim 14 (depends on 11)

The method according to claim 11, wherein providing the first region at the first section of the channel region comprises:
providing the first region over a substrate to form a combined structure;
bonding at least a portion of the combined structure to the first section of the channel region; and
removing the substrate.

### Claim 15 (depends on 11)

The method according to claim 11, wherein the first semiconductor material is the same as the second semiconductor material.

### Claim 16

An integrated circuit (IC) device, comprising:
a substrate;
a first transistor arrangement, comprising:
a first region, comprising a first semiconductor material with dopants of a first type,
a second region, comprising a second semiconductor material with dopants of the first type, and
a channel region, the channel region crossing the substrate; and
a second transistor arrangement, comprising:
the first region,
the channel region, and
a third region, comprising a third semiconductor material with dopants of a second type, wherein the second type is different from the first type,
wherein the first region, the second region, and the third region are connected to the channel region.

### Claim 17 (depends on 16)

The IC device according to claim 16, further comprising:
a first gate electrode over a first portion of the channel region, wherein the first portion of the channel region is between the first region and the second region; and
a second gate electrode over a second portion of the channel region, wherein the second portion of the channel region is between the first region and the third region.

### Claim 18 (depends on 17)

The IC device according to claim 17, wherein the first gate electrode wraps around the first portion of the channel region, or the second gate electrode wraps around the second portion of the channel region

### Claim 19 (depends on 17)

The IC device according to claim 17, further comprising:
a first insulator between the first gate electrode and the first region or the second region; and
a second insulator between the second gate electrode and the first region or the third region.

### Claim 20 (depends on 17)

The IC device according to claim 17, further comprising:
a first insulator between the first gate electrode and the first portion of the channel region; and
a second insulator between the second gate electrode and the second portion of the channel region.