# US 2023/0275083 A1 · Forksheet semiconductor structure including at least one bipolar junction transistor and method

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- Number: US 2023/0275083 A1
- Document ID: US20230275083A1
- Status: Published application
- Kind: A1
- Application number: 17/807,899
- Filed: 2022-06-21
- Published: 2023-08-31
- Earliest claimed: 2022-02-28
- Assignees: GlobalFoundries U.S. Inc.
- Applicants: GlobalFoundries U.S. Inc.
- Inventors: Arkadiusz Malinowski; Alexander M. Derrickson
- Web page: https://patentgrep.com/patent/US20230275083A1

## CPC

- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10D 84/645: {Combinations of only lateral BJTs}
- H10D 10/061: {of lateral BJTs (of heterojunction BJTs H10D10/021; of thin film BJTs H10D10/041)}
- H10D 10/60: Lateral BJTs
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device}
- H10D 84/0112: {Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs}
- H10D 84/0119: {the components including complementary BJTs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3462: {Nanowires}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Disclosed are a forksheet semiconductor structure and a method of forming the structure. The structure can include a dielectric body with a first sidewall and a second sidewall opposite the first sidewall. The structure can include a first transistor, which incorporates first semiconductor nanosheet(s) positioned laterally immediately adjacent to the first sidewall of the dielectric body, and a second transistor, which incorporates second semiconductor nanosheet(s) positioned laterally immediately adjacent to the second sidewall. The first transistor and the second transistor can both be bipolar junction transistors (BJTs) (e.g., PNP-type BJTs, NPN-type BJTs or a PNP-type BJT and an NPN-type BJT). Alternatively, the first transistor can be a BJT (e.g., a PNP-type BJT or an NPN-type BJT) and the second transistor can be a field effect transistor (FET) (e.g., an N-type FET (NFET) or a P-type FET (PFET)).

## Claims

### Claim 1

A structure comprising:
a dielectric body having a first sidewall and a second sidewall opposite the first sidewall;
a first transistor comprising a first semiconductor nanosheet positioned laterally immediately adjacent to the first sidewall; and
a second transistor comprising a second semiconductor nanosheet positioned laterally immediately adjacent to the second sidewall, wherein at least the first transistor comprises a bipolar junction transistor.

### Claim 2 (depends on 1)

The structure of claim 1,
wherein the first semiconductor nanosheet further has a first bottom surface, a first top surface opposite the first bottom surface, a first proximal side immediately adjacent to the first sidewall of the dielectric body, and a first distal side opposite the first proximal side, and wherein the first transistor comprises:
a base region comprising:
the first semiconductor nanosheet;
a base semiconductor layer adjacent to the first bottom surface, the first distal side, and the first top surface; and
an additional base semiconductor layer on the base semiconductor layer; and
emitter/collector regions, wherein the base region is positioned laterally between the emitter/collector regions.

### Claim 3 (depends on 2)

The structure of claim 2, further comprising:
a dielectric layer on the first transistor and the second transistor and further extending over and immediately adjacent to the dielectric body; and
contacts extending through the dielectric layer to the first transistor and the second transistor.

### Claim 4 (depends on 2)

The structure of claim 2, wherein the base semiconductor layer has a first-type conductivity, wherein the additional base semiconductor layer has the first-type conductivity at a higher first-type conductivity level than the base semiconductor layer, and wherein the emitter/collector regions have a second-type conductivity that is different from the first-type conductivity.

### Claim 5 (depends on 4)

The structure of claim 4, wherein the first semiconductor nanosheet is any of an intrinsic semiconductor nanosheet and a first-type conductivity semiconductor nanosheet.

### Claim 6 (depends on 1)

The structure of claim 1, wherein the second transistor comprises a field effect transistor.

### Claim 7 (depends on 6)

The structure of claim 6,
wherein the second semiconductor nanosheet further has a second bottom surface, a second top surface opposite the second bottom surface, a second proximal side immediately adjacent to the second sidewall, and a second distal side opposite the second proximal side, and
wherein the field effect transistor comprises:
a channel region comprising the second semiconductor nanosheet;
a gate structure comprising:
a gate dielectric layer adjacent to the second bottom surface, the second distal side, and the second top surface; and
a gate conductor layer on the gate dielectric layer opposite the second bottom surface, the second distal side, and the second top surface; and
source/drain regions, wherein the second semiconductor nanosheet is positioned laterally between and immediately adjacent to the source/drain regions and wherein the gate conductor layer is electrically isolated from the source/drain regions.

### Claim 8 (depends on 7)

The structure of claim 7, wherein the bipolar junction transistor and the field effect transistor comprise one:
a PNP-type bipolar junction transistor and a P-type field effect transistor;
a PNP-type bipolar junction transistor and an N-type field effect transistor;
an NPN-type bipolar junction transistor and a P-type field effect transistor; and
an NPN-type bipolar junction transistor and an N-type field effect transistor.

### Claim 9

A structure comprising:
a dielectric body having a first sidewall and a second sidewall opposite the first sidewall;
a first bipolar junction transistor comprising a first semiconductor nanosheet positioned laterally immediately adjacent to the first sidewall; and
a second bipolar junction transistor comprising a second semiconductor nanosheet positioned laterally immediately adjacent to the second sidewall.

### Claim 10 (depends on 9)

The structure of claim 9, further comprising:
a semiconductor substrate; and
an isolation region in the semiconductor substrate,
wherein the dielectric body is above and immediately adjacent to the isolation region,
wherein the isolation region is positioned laterally between a first semiconductor body and a second semiconductor body in an upper portion of the semiconductor substrate,
wherein the first semiconductor nanosheet is aligned above and physically separated from the first semiconductor body, and
wherein the second semiconductor nanosheet is aligned above and physically separated from the second semiconductor body.

### Claim 11 (depends on 9)

The structure of claim 9,
wherein the first semiconductor nanosheet further has a first bottom surface, a first top surface opposite the first bottom surface, a first proximal side immediately adjacent to the first sidewall, and a first distal side opposite the first proximal side,
wherein the first bipolar junction transistor comprises:
a first base region comprising:
the first semiconductor nanosheet;
a first base semiconductor layer adjacent to the first bottom surface, the first distal side, and the first top surface; and
an additional first base semiconductor layer on the first base semiconductor layer; and
first emitter/collector regions, wherein the first base region is positioned laterally between the first emitter/collector regions,
wherein the second semiconductor nanosheet further has a second bottom surface, a second top surface opposite the second bottom surface, a second proximal side immediately adjacent to the second sidewall, and a second distal side opposite the second proximal side, and
wherein the second bipolar junction transistor comprises:
a second base region comprising:
the second semiconductor nanosheet;
a second base semiconductor layer adjacent to the second bottom surface, the second distal side, and the second top surface; and
an additional second base semiconductor layer on the second base semiconductor layer;
second emitter/collector regions, wherein the second base region is positioned laterally between the second emitter/collector regions.

### Claim 12 (depends on 11)

The structure of claim 11, wherein the first bipolar junction transistor and the second bipolar junction transistor comprise NPN-type bipolar junction transistors.

### Claim 13 (depends on 11)

The structure of claim 11, wherein the first bipolar junction transistor and the second bipolar junction transistor comprise PNP-type bipolar junction transistors.

### Claim 14 (depends on 11)

The structure of claim 11, wherein the first bipolar junction transistor comprises a PNP-type bipolar junction transistor and the second bipolar junction transistor comprises an NPN-type bipolar junction transistor.

### Claim 15 (depends on 11)

The structure of claim 11, further comprising:
a dielectric layer on the first bipolar junction transistor and the second bipolar junction transistor and further extending laterally over and immediately adjacent to the dielectric body electrically isolating the first bipolar junction transistor from the second bipolar junction transistor; and
contacts extending through the dielectric layer to the first bipolar junction transistor and the second bipolar junction transistor.

### Claim 16

A method comprising:
forming a first transistor comprising a first semiconductor nanosheet positioned laterally immediately adjacent to a first sidewall of a dielectric body; and
forming a second transistor comprising a second semiconductor nanosheet positioned laterally immediately adjacent to a second sidewall of the dielectric body opposite the first sidewall,
wherein the forming of the first transistor comprises forming a bipolar junction transistor.

### Claim 17 (depends on 16)

The method of claim 16, wherein the forming of the second transistor comprises forming a second bipolar junction transistor.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first transistor and the second transistor are formed so as to comprise one of:
two PNP-type bipolar junction transistors;
two NPN-type bipolar junction transistors; and
a PNP-type bipolar junction transistor and an NPN-type bipolar junction transistor.

### Claim 19 (depends on 16)

The method of claim 16, wherein the forming of the second transistor comprises forming a field effect transistor.

### Claim 20 (depends on 19)

The method of claim 19, wherein the first transistor and the second transistor are formed so as to comprise one of:
a PNP-type bipolar junction transistor and a P-type field effect transistor;
a PNP-type bipolar junction transistor and an N-type field effect transistor;
an NPN-type bipolar junction transistor and a P-type field effect transistor; and
an NPN-type bipolar junction transistor and an N-type field effect transistor.