# US 2023/0274682 A1 · Digital gray control in display systems

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- Number: US 2023/0274682 A1
- Document ID: US20230274682A1
- Status: Published application
- Kind: A1
- Application number: 17/961,857
- Filed: 2022-10-07
- Published: 2023-08-31
- Earliest claimed: 2022-02-28
- Assignees: Meta Platforms Technologies, LLC
- Applicants: Meta Platforms Technologies, LLC
- Inventors: Yun WANG
- Web page: https://patentgrep.com/patent/US20230274682A1

## CPC

- G09G 3/2007: {Display of intermediate tones}
- G09G 3/3275: Details of drivers for data electrodes
- G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element
- G09G 3/2014: {by modulation of the duration of a single pulse during which the logic level remains constant}
- G09G 3/2022: {using sub-frames}
- G09G 2300/0814: used for selection purposes, e.g. logical AND for partial update
- G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G 2300/0857: Static memory circuit, e.g. flip-flop
- G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
- G09G 2310/0294: Details of sampling or holding circuits arranged for use in a driver for data electrodes
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2330/021: Power management, e.g. power saving
- G09G 2360/18: Use of a frame buffer in a display terminal, inclusive of the display panel
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

According to some examples, a display system may include control circuitry, power supply circuitry, and a pixel array. Each pixel in the pixel array may include a data shift register to receive gray level data for the pixel in series and to output the gray level data in parallel. Each pixel may also include a plurality of comparators, each comparator of the plurality of comparators to receive one bit of data from the data shift register and one bit of clock data, and a NOR gates sum circuit to provide a binary output based on outputs of all of the plurality of comparators. Each pixel may further include a flip flop circuit to provide a binary output based on the binary output of the NOR gates sum circuit, and an emissions circuit to emit light at a selected gray level based on the binary output of the flip flop circuit.

## Claims

### Claim 1

A display system, comprising:
control circuitry;
power supply circuitry; and
a pixel array, wherein each pixel in the pixel array comprises:
a data shift register to receive gray level data for the pixel in series and to output the gray level data in parallel;
a plurality of comparators, each comparator of the plurality of comparators to receive one bit of data from the data shift register and one bit of clock data;
a NOR gates sum circuit to provide a binary output based on outputs of all of the plurality of comparators;
a flip flop circuit to provide a binary output based on the binary output of the NOR gates sum circuit; and
an emissions circuit to emit light at a selected gray level based on the binary output of the flip flop circuit.

### Claim 2 (depends on 1)

The display system of claim 1, wherein the emission circuit comprises:
an emission transistor controlled by the binary output of the flip flop circuit;
a drive transistor serially coupled to the emission transistor and to act as a current source; and
an emission diode serially coupled to the drive transistor and to emit the light at the selected gray level.

### Claim 3 (depends on 1)

The display system of claim 1, further comprising:
an embedded frame buffer to store gray level data for a row of pixels, wherein the embedded frame buffer is to provide the gray level data to the pixel array row by row.

### Claim 4 (depends on 1)

The display system of claim 1, wherein the NOR gates sum circuit is to:
provide a “1” output if outputs of all of the plurality of comparators indicate a match; and
provide a “0” output if at least one output of the plurality of comparators indicates a mismatch.

### Claim 5 (depends on 1)

The display system of claim 1, wherein the flip flop circuit is a set-reset (SR) flip flop and to:
turn off an emission transistor of the emission circuit if the binary output of the NOR gates sum circuit is a “1”; and
turn on the emission transistor of the emission circuit if the binary output of the NOR gates sum circuit is a “0”.

### Claim 6 (depends on 1)

The display system of claim 1, wherein each of the plurality of comparators comprises an XOR gate and is to:
provide a “0” output if the one bit of data from the data shift register and one bit of clock data from the external clock match; and
provide a “1” output if the one bit of data from the data shift register and one bit of clock data from the external clock mismatch.

### Claim 7 (depends on 1)

The display system of claim 1, wherein the display system is an organic light emitting diode (OLED) display system, a microLED, liquid-crystal on silicon (LCOS), or a digital driving control-based display system.

### Claim 8 (depends on 1)

The display system of claim 1, further comprising:
a clock circuit to provide the clock data to the plurality of comparators of each pixel.

### Claim 9 (depends on 1)

The display system of claim 1, wherein the data shift register, the plurality of comparators, the NOR gates sum circuit, and the flip flop circuit are integrated with circuits of the display system external to the pixel array in a single CMOS backplane.

### Claim 10 (depends on 1)

The display system of claim 1, wherein each pixel in the pixel array further comprises a storage capacitor coupled between a source terminal and a gate terminal of the drive transistor.

### Claim 11 (depends on 1)

The display system of claim 1, wherein the data shift register and a clock circuit of the display system providing the clock data are to receive an enable signal to enable activation of one or more groups of pixels in the pixel array without black content.

### Claim 12

A method to make a display system, the method comprising:
disposing one or more of control circuitry and power supply circuitry on a substrate; and
disposing a pixel array comprising a plurality of pixels on the substrate by:
disposing a data shift register for each pixel on the substrate, the data shift register to receive gray level data for that pixel in series and to output the gray level data in parallel;
disposing a plurality of comparators for each pixel on the substrate, each comparator of the plurality of comparators to receive one bit of data from the data shift register and one bit of clock data;
disposing a NOR gates sum circuit for each pixel on the substrate, the NOR gates sum circuit to provide a binary output based on outputs of all of the plurality of comparators for that pixel;
disposing a flip flop circuit for each pixel on the substrate, the flip flop circuit to provide a binary output based on the binary output of the NOR gates sum circuit;
disposing an emission transistor for each pixel on the substrate, the emission transistor controlled by the binary output of the flip flop circuit; and
disposing a drive transistor serially coupled to the emission transistor for each pixel on the substrate, the drive transistor to act as a current source.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
disposing an embedded frame buffer on the substrate, the embedded frame buffer to store gray level data for a row of pixels provide the gray level data to each pixel array row by row.

### Claim 14 (depends on 12)

The method of claim 12, further comprising:
disposing a clock circuit on the substrate, the clock circuit to provide the clock data to the plurality of comparators of each pixel.

### Claim 15 (depends on 12)

The method of claim 12, further comprising:
providing a connection for an enable signal to the data shift register and a clock circuit of the display system to enable activation of one or more groups of pixels in the pixel array without black content; or
disposing a storage capacitor for each pixel in the pixel array, the storage capacitor coupled between a source terminal and a gate terminal of each drive transistor.

### Claim 16 (depends on 12)

The method of claim 12, wherein the display system is an organic light emitting diode (OLED) display system, and the method further comprises:
forming an OLED emission film that includes a substrate, an anode layer, a conductive layer, an emissive layer, and a cathode layer, the OLED emission film including a plurality of emission diodes corresponding to the plurality of pixels;
forming the one or more of control circuitry, the power supply circuitry, and the pixel array as a single CMOS backplane; and
coupling the OLED emission film and the CMOS backplane.

### Claim 17

A method to operate a digital driving control-based display system, the method comprising:
receiving gray level data at a data shift register for each pixel in a pixel array in series;
outputting the gray level data from the data shift register in parallel;
receiving one bit of the gray level data from the data shift register and one bit of clock data from a clock at each of a plurality of comparators;
providing a comparison of the one bit of the gray level data and the one bit of clock data from a clock for each pixel to a NOR gates sum circuit;
providing a binary output based on comparison outputs of all of the plurality of comparators for a pixel to a flip flop circuit; and
providing a binary output from the flip flop circuit to control an emission transistor for the pixel based on the binary output of the NOR gates sum circuit, wherein the emission transistor controls activation of an emission circuit for the pixel.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
receiving the gray level data at the data shift register from an embedded frame buffer, wherein the embedded frame buffer is to store the gray level data for a row of pixels and to provide the gray level data to each pixel array row by row.

### Claim 19 (depends on 17)

The method of claim 17, further comprising:
controlling the activation of the emission circuit for the pixel by turning on and off the emission transistor, wherein the emission transistor is coupled in series with a driving transistor that acts as a current source for an emission diode.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
receiving an enable signal at the data shift register and the clock to activate one or more groups of pixels in the pixel array without black content.