# US 2023/0273668 A1 · Semiconductor memory device, electronic device and method for setting the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0273668 A1 - Document ID: US20230273668A1 - Status: Published application - Kind: A1 - Application number: 18/144,956 - Filed: 2023-05-09 - Published: 2023-08-31 - Earliest claimed: 2019-10-08 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Ki-Seok OH - Web page: https://patentgrep.com/patent/US20230273668A1 ## CPC - G06F 1/3275: {Power saving in memory, e.g. RAM, cache} - G11C 7/1045: {Read-write mode select circuits} - G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory - G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/409: Read-write [R-W] circuits - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - G11C 2207/2272: Latency related aspects - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract An electronic device includes a semiconductor memory device configured to store process information and to output the process information to the outside; and a host configured to read the process information from the semiconductor memory device, and to select one of a plurality of operation modes depending on the process information so as to be set to an operation mode of the semiconductor memory device. The plurality of operation modes may define one or more of power consumption of the semiconductor memory device or a response characteristic of the semiconductor memory device. ## Claims ### Claim 1 An electronic device, comprising: a semiconductor memory device configured to store process information and to output the process information to outside of the semiconductor memory device, the process information being programmed in the semiconductor memory device as a part of a process of manufacturing the semiconductor memory device and indicating whether the process used to manufacture the semiconductor memory device is a legacy process or an enhanced process which provides higher device performance than the legacy process; and a host configured to read the process information from the semiconductor memory device, to select a target operation mode from among a plurality of operation modes depending on the process information, and to set an operation mode of the semiconductor memory device based on the selected target operation mode, wherein: the plurality of operation modes define a plurality of respectively different latencies, by which data are output from the semiconductor memory device in response to a read command, the plurality of respectively different latencies include a first latency and a second latency, the second latency being longer than the first latency, and the host is further configured to select, from among the plurality of operation modes, a first operation mode corresponding to the first latency in response to the process information indicating the enhanced process as the target operation mode, and to select, from among the plurality of operation modes, a second operation mode corresponding to the second latency in response to the process information indicating the legacy process as the target operation mode. ### Claim 2 (depends on 1) The electronic device as claimed in claim 1, wherein the enhanced process corresponds to a high-K metal gate process or a fin field effect transistor process. ### Claim 3 (depends on 1) The electronic device as claimed in claim 1, wherein the device performance indicates at least one of a voltage level, a clock frequency, and a latency. ### Claim 4 (depends on 1) The electronic device as claimed in claim 1, wherein the plurality of operation modes include: a third operation mode, in which the semiconductor memory device is set by the host to operate at a third latency and a first voltage level, a fourth operation mode, in which the semiconductor memory device is set by the host to operate at the third latency and a second voltage level, the second voltage level being less than the first voltage level, and a fifth operation mode, in which the semiconductor memory device is set by the host to operate at a fourth latency and the first voltage level, the fourth latency being less than the third latency. ### Claim 5 (depends on 1) The electronic device as claimed in claim 1, wherein the process information corresponds to the process used to manufacture a peripheral circuit to control a cell array of the semiconductor memory device. ### Claim 6 (depends on 1) The electronic device as claimed in claim 1, wherein the semiconductor memory device includes a program component for storing the process information. ### Claim 7 (depends on 1) The electronic device as claimed in claim 1, wherein the process information is output through a mode register read by the host. ### Claim 8 (depends on 1) The electronic device as claimed in claim 1, wherein, when the process information corresponds to the enhanced process, the host is further configured to set the operation mode of the semiconductor memory device with an operation parameter corresponding to the selected first operation mode. ### Claim 9 (depends on 8) The electronic device as claimed in claim 8, wherein the host is further configured to perform a training operation for optimizing a reference voltage level and a timing of the semiconductor memory device set with the operation parameter. ### Claim 10 (depends on 1) The electronic device as claimed in claim 1, wherein the semiconductor memory device includes a mode register set storing information about one or more of an operating voltage level or an operating speed corresponding to the selected target operation mode. ### Claim 11 A method for setting a semiconductor memory device, the method comprising: reading, by a host, process information from the semiconductor memory device, the process information being programmed in the semiconductor memory device as a part of a process of manufacturing the semiconductor memory device; performing, by the host, a determination on whether the process information indicates a legacy process or an enhanced process which provides higher device performance than the legacy process; selecting, by the host, a target operation mode from among a plurality of operation modes, depending on the determination; and setting, by the host, an operation mode of the semiconductor memory device based on the selected target operation mode, wherein: the plurality of operation modes define a plurality of respectively different latencies, by which data are output from the semiconductor memory device in response to a read command, the plurality of respectively different latencies include a first latency and a second latency, the second latency being longer than the first latency, and the method further comprises selecting, by the host, a first operation mode corresponding to the first latency from among the plurality of operation modes in response to the process information indicating the enhanced process as the target operation mode, and selecting, by the host, a second operation mode corresponding to the second latency from among the plurality of operation modes in response to the process information indicating the legacy process as the target operation mode. ### Claim 12 (depends on 11) The method as claimed in claim 11, wherein the enhanced process corresponds to a high-K metal gate process or a fin field effect transistor process. ### Claim 13 (depends on 11) The method as claimed in claim 11, wherein the device performance indicates at least one of a voltage level, a clock frequency, and a latency. ### Claim 14 (depends on 11) The method as claimed in claim 11, wherein the plurality of operation modes include: a third operation mode, in which the semiconductor memory device is set by the host to operate at a third latency and a first voltage level, a fourth operation mode, in which the semiconductor memory device is set by the host to operate at the third latency and a second voltage level, the second voltage level being less than the first voltage level, and a fifth operation mode, in which the semiconductor memory device is set by the host to operate at a fourth latency and the first voltage level, the fourth latency being less than the third latency. ### Claim 15 (depends on 11) The method as claimed in claim 11, wherein: the semiconductor memory device includes a cell array in which the data are stored, and a peripheral circuit configured to control the cell array and to control an input/output of the data, and the process information corresponds to a process used to manufacture the peripheral circuit. ### Claim 16 (depends on 11) The method as claimed in claim 11, wherein the reading of the process information is performed by a mode register read for reading the process information stored in a mode register set of the semiconductor memory device. ### Claim 17 (depends on 11) The method as claimed in claim 11, wherein the reading of the process information is performed by a control operation for reading the process information programmed at a nonvolatile memory element provided in the semiconductor memory device. ### Claim 18 (depends on 11) The method as claimed in claim 11, wherein the semiconductor memory device includes a dedicated pin for outputting the process information. ### Claim 19 (depends on 11) The method as claimed in claim 11, further comprising performing a training operation for optimizing a reference voltage level and a timing of the semiconductor memory device, after a mode register set of the semiconductor memory device is set. ### Claim 20 A semiconductor memory device, comprising: a cell array including a plurality of DRAM cells to store data; a peripheral circuit configured to write data in the cell array, or to sense and output data stored in the cell array; and a mode register set circuit configured to output process information about the peripheral circuit to a host, and to set a target output latency of data, from among a plurality of respectively different latencies, in response to a mode register write request from the host, wherein: the process information is programmed in the semiconductor memory device as a part of a process of manufacturing the semiconductor memory device and indicates whether the process used to manufacture the semiconductor memory device is a legacy process or an enhanced process which provides higher device performance than the legacy process, the plurality of respectively different latencies include a first latency and a second latency, the second latency being longer than the first latency, and the mode register set circuit is configured to, in response to the mode register write request from the host, set a first output latency of data according to the first latency in response to the process information indicating the enhanced process as the target output latency, and set a second output latency of data according to the second latency in response to the process information indicating the legacy process as the target output latency.