# US 2023/0273666 A1 · Interface circuit for controlling output impedance of a transmission circuit and an image sensor including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2023/0273666 A1 - Document ID: US20230273666A1 - Status: Published application - Kind: A1 - Application number: 18/142,700 - Filed: 2023-05-03 - Published: 2023-08-31 - Earliest claimed: 2021-02-03 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Chaeryung KIM; Kiwoon KIM; Jiun JEONG; Hoyoung KIM; Dongjun PARK; Dongyoung SONG; Kyuik CHO; Gyeonghan CHA - Web page: https://patentgrep.com/patent/US20230273666A1 ## CPC - G06F 1/3253: {Power saving in bus} - G06F 1/1686: {the I/O peripheral being an integrated camera} - G06F 1/3215: Monitoring of peripheral devices - G06F 1/3278: {Power saving in modem or I/O interface} - G06F 1/3287: by switching off individual functional units in the computer system - G06F 13/4068: {Electrical coupling} - G06F 13/4086: {Bus impedance matching, e.g. termination} - G06F 1/266: {Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips} - H04N 23/57: Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract An interface circuit including: a first transmission circuit outputting a first signal to a transmission line via first transfer pads; and a second transmission circuit outputting a second signal to the transmission line via second transfer pads, the first transmission circuit includes a first termination resistor block including a switch and a first termination resistor connected between the first transfer pads, the second transmission circuit includes a second termination resistor block including a switch and a second termination resistor connected between the second transfer pads, and when the first transmission circuit outputs the first signal, the second termination resistor block detects the first signal, and when the first transmission circuit is in a low-power operation mode, the second termination resistor block disconnects the second termination resistor, and when the first transmission circuit is in a high-speed data transfer mode, the second termination resistor block connects the second termination resistor. ## Claims ### Claim 1 An image sensor comprising: a pixel array configured to generate electric charges in response to light; a logic circuit configured to convert the electric charges into first image data; and an interface circuit configured to transmit the first image data to an external processor via a first transmission line and a second transmission line, wherein the interface circuit is configured to connect the first transmission line and the second transmission line when the interface circuit does not transmit the first image data to the external processor. ### Claim 2 (depends on 1) The image sensor of claim 1, wherein the interface circuit is configured to transmit the first image data in accordance with a MIPI standard. ### Claim 3 (depends on 2) The image sensor of claim 2, wherein the interface circuit is configured to monitor statuses of the first transmission line and the second transmission line, and wherein the interface circuit is configured to connect or disconnect the first transmission line and the second transmission line based on a monitoring result. ### Claim 4 (depends on 2) The image sensor of claim 2, wherein the MIPI standard is a MIPI D-PHY. ### Claim 5 (depends on 4) The image sensor of claim 4, wherein the interface circuit is configured to connect the first transmission line and the second transmission line when the interface circuit detects transmission of second image data, different from the first image data, via the first transmission line and the second transmission line. ### Claim 6 (depends on 3) The image sensor of claim 3, wherein the interface circuit comprises a first resistor disposed between the first transmission line and the second transmission line, and wherein the first transmission line and the second transmission line are connected via the first resistor when the interface circuit does not transmit the first image data to the external processor. ### Claim 7 (depends on 6) The image sensor of claim 6, wherein the interface circuit further comprises a first switch and a control logic, and wherein the control logic is configured to control the first switch to connect or disconnect the first transmission line and the second transmission line via the first resistor. ### Claim 8 (depends on 7) The image sensor of claim 7, wherein the interface circuit further comprises a second switch and a second resistor, and wherein the control logic is configured to control the first switch and the second switch to connect the first transmission line and the second transmission line via the first resistor and the second resistor. ### Claim 9 An image sensor comprising: a pixel array configured to generate electric charges in response to light; a logic circuit configured to convert the electric charges into image data; and an interface circuit configured to transmit the image data to an external processor via a first transmission line and a second transmission line in accordance with a MIPI D-PHY, wherein the interface circuit is configured to connect the first transmission line and the second transmission line. ### Claim 10 (depends on 9) The image sensor of claim 9, wherein the interface circuit is configured to transmit the image data as a frame unit or a line unit of the pixel array. ### Claim 11 (depends on 10) The image sensor of claim 10, wherein the interface circuit is configured to connect the first transmission line and the second transmission line when the interface circuit does not transmit the image data to the external processor. ### Claim 12 (depends on 10) The image sensor of claim 10, wherein the interface circuit comprises a first switch and a first resistor, and wherein the first transmission line and the second transmission line are connected via the first switch and the first resistor. ### Claim 13 (depends on 12) The image sensor of claim 12, wherein the interface circuit is configured to monitor statuses of the first transmission line and the second transmission line, and wherein the interface circuit is configured to connect the first transmission line and t second transmission line based on a monitoring result. ### Claim 14 (depends on 12) The image sensor of claim 12, wherein the interface circuit further comprises a second switch and a second resistor, and wherein the first transmission line and the second transmission line are connected via the first switch, the first resistor, the second switch and the second resistor. ### Claim 15 (depends on 14) The image sensor of claim 14, wherein the first switch, the first resistor, the second resistor and the second switch are sequentially connected. ### Claim 16 An image sensor comprising: a pixel array configured to generate electric charges in response to light; a logic circuit configured to convert the electric charges into first image data; and an interface circuit configured to transmit the first image data to an external processor via a first transmission line and a second transmission line in accordance with a MIPI D-PHY, wherein the interface circuit is configured to adjust an impedance of the first transmission line when the interface circuit detects transmission of second image data, different from the first image data, via the first transmission line and the second transmission line. ### Claim 17 (depends on 16) The image sensor of claim 16, wherein the interface circuit is configured to connect the first transmission line and the transmission line to adjust the impedance. ### Claim 18 (depends on 17) The image sensor of claim 17, wherein the interface circuit is configured to connect the first transmission line to the second transmission line via a switch and a resistor.