# US 2023/0273632 A1 · Proportional to absolute temperature (ptat) voltage generating circuit for generating a ptat voltage and acts as a temperature sensor

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- Number: US 2023/0273632 A1
- Document ID: US20230273632A1
- Status: Published application
- Kind: A1
- Application number: 18/115,649
- Filed: 2023-02-28
- Published: 2023-08-31
- Earliest claimed: 2022-02-28
- Assignees: International Institute of Information Technology, Hyderabad
- Applicants: International Institute of Information Technology, Hyderabad
- Inventors: Zia Abbas; Abhishek Pullela; Ashfakh Ali; Arpan Jain
- Web page: https://patentgrep.com/patent/US20230273632A1

## CPC

- G05F 1/56: using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence)
- G05F 3/30: Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities (G05F3/26 takes precedence)
- G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES

## Abstract

A proportional to-absolute-temperature (PTAT) voltage generating circuit connected between a power supply voltage source and a ground for providing a PTAT voltage at an output terminal of the PTAT voltage generating circuit to act as a temperature sensor is provided. The PTAT voltage generating circuit includes a plurality of PMOS transistors. The plurality of PMOS transistors generates a second PTAT voltage by multiplying a first PTAT voltage by a factor equal to a ratio of a first equivalent resistance (R2) and a second resistance (R1) of a first PMOS transistor (M4). The first equivalent resistance (R2) is obtained from a series combination of the plurality of PMOS transistors. The first PTAT voltage is generated by determining a difference between a base-emitter voltage of a first PNP transistor (T1) and the second PNP transistor (T2).

## Claims

### Claim 1

A proportional to-absolute-temperature (PTAT) voltage generating circuit connected between a power supply voltage source and a ground for providing a PTAT voltage at an output terminal of the PTAT voltage generating circuit to act as a temperature sensor, comprising:
a first P-channel metal oxide semiconductor (PMOS) transistor (M4) that comprises a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal of the first PMOS transistor (M4) is connected to a collector of a second PNP transistor (T2),
wherein the second PNP transistor (T2) generates a first PTAT voltage by determining a difference between a base-emitter voltage of a first PNP transistor (T1) and the second PNP transistor (T2), wherein an emitter of the first PNP transistor (T1) is connected to a first input terminal of a differential amplifier, and an emitter of the second PNP transistor (T2) is connected to a second input terminal of the differential amplifier,
wherein the first PTAT voltage is amplified by multiplying by a factor that is equal to a ratio of a first equivalent resistance (R2) and a second resistance (R1) of the first PMOS transistor (M4) to generate a second PTAT voltage,
wherein the first equivalent resistance (R2) is obtained from a series combination of a second PMOS transistor (M5), a third PMOS transistor (M6), a fourth PMOS transistor (M7), a fifth PMOS transistor (M8), a sixth PMOS transistor (M9), and a seventh PMOS transistor (M10), wherein the second PTAT voltage is temperature invariant and thereby, the PTAT voltage generating circuit act as the temperature sensor.

### Claim 2 (depends on 1)

The PTAT voltage generating circuit of claim 1, wherein the first PMOS transistor (M4), the second PMOS transistor (M5), the third PMOS transistor (M6), the fourth PMOS transistor (M7), the fifth PMOS transistor (M8), the sixth PMOS transistor (M9), and the seventh PMOS transistor (M10) generate a gate-leakage current that applies a square-law with respect to temperature, thereby enabling the PTAT voltage generating circuit to sense low temperatures down to -40° C.

### Claim 3 (depends on 1)

The PTAT voltage generating circuit of claim 1, wherein the PTAT voltage generating circuit is connected to a start-up circuit and a gate-leakage-based beta-multiplier circuit, wherein the start-up circuit and the gate-leakage-based beta-multiplier circuit are employed for a feedback loop, thereby avoiding degenerating bias points in the temperature sensor.

### Claim 4 (depends on 1)

The PTAT voltage generating circuit of claim 1, wherein tunneling current of the first PMOS transistor (M4), the second PMOS transistor (M5), the third PMOS transistor (M6), the fourth PMOS transistor (M7), the fifth PMOS transistor (M8), the sixth PMOS transistor (M9), and the seventh PMOS transistor (M10) vary with a temperature that depends on gate-source voltage, wherein the tunneling current range from Femto Amperes (fA) to pico Amperes (pA).

### Claim 5 (depends on 1)

The PTAT voltage generating circuit of claim 1, wherein the PTAT voltage generating circuit comprises an eighth PMOS transistor (M1), a ninth PMOS transistor (M2), and a tenth PMOS transistor (M3), each having a gate terminal, a source terminal, and a drain terminal wherein a gate terminal of the eighth PMOS transistor (M1), the ninth PMOS transistor (M2), and the tenth PMOS transistor (M3) are coupled to an output terminal of the differential amplifier, wherein a source terminal of the eighth PMOS transistor (M1), the ninth PMOS transistor (M2), and the tenth PMOS transistor (M3) are coupled to a power supply voltage source, wherein a drain terminal of the eighth PMOS transistor (M1) is connected to a first input terminal of the differential amplifier, wherein a drain terminal of the ninth PMOS transistor (M2) is connected to a second input terminal of the differential amplifier, wherein a drain terminal of the tenth PMOS transistor (M3) is coupled to an output terminal of the PTAT voltage generating circuit, wherein the eighth PMOS transistor (M1), the ninth PMOS transistor (M2), and the tenth PMOS transistor (M3) mirrors the first PTAT voltage at the series combination.

### Claim 6 (depends on 5)

The PTAT voltage generating circuit of claim 5, wherein tunneling currents of the eighth PMOS transistor (M1), the ninth PMOS transistor (M2), and the tenth PMOS transistor (M3) vary with a temperature that depends on gate-source voltage, wherein the tunneling currents range from Femto Amperes (fA) to pico Amperes (pA).

### Claim 7

A PTAT voltage generating circuit connected between a power supply voltage source and a ground for providing a PTAT voltage at an output terminal of the PTAT voltage generating circuit to act as a temperature sensor, comprising:
a plurality of PMOS transistors, that generates a second PTAT voltage by multiplying a first PTAT voltage by a factor equal to a ratio of a first equivalent resistance (R2) that is obtained from a series combination of the plurality of PMOS transistors and a second resistance (R1) of a first PMOS transistor (M4), wherein the first PTAT voltage is generated by determining a difference between a base-emitter voltage of a first PNP transistor (T1) and the second PNP transistor (T2).

### Claim 8 (depends on 7)

The PTAT voltage generating circuit of claim 7, wherein the plurality of PMOS transistors comprise the first PMOS transistor (M4), a second PMOS transistor (M5), and a third PMOS transistor (M6), a fourth PMOS transistor (M7), a fifth PMOS transistor (M8), a sixth PMOS transistor (M9), and a seventh PMOS transistor (M10), wherein the series combination comprises the second PMOS transistor (M5), the third PMOS transistor (M6), the fourth PMOS transistor (M7), the fifth PMOS transistor (M8), the sixth PMOS transistor (M9), and the seventh PMOS transistor (M10).

### Claim 9 (depends on 7)

The PTAT voltage generating circuit of claim 7, wherein the plurality of PMOS transistors comprise an eighth PMOS transistor (M1), a ninth PMOS transistor (M2), and a tenth PMOS transistor (M3) that are connected to a differential amplifier mirrors the first PTAT voltage at the series combination.

### Claim 10 (depends on 7)

The PTAT voltage generating circuit of claim 7, wherein the plurality of PMOS transistors generate a gate-leakage current that applies a square-law with respect to temperature, thereby the PTAT voltage generating circuit senses low temperatures down to -40° C.

### Claim 11 (depends on 7)

The PTAT voltage generating circuit of claim 7, wherein the PTAT voltage generating circuit is connected with a start-up circuit and a gate-leakage-based beta-multiplier circuit, wherein the start-up circuit and the gate-leakage-based beta-multiplier circuit are used for a feedback loop to avoid degenerating bias points in the temperature sensor.

### Claim 12 (depends on 6)

The PTAT voltage generating circuit of claim 6, wherein tunneling currents of the plurality of PMOS transistors vary with a temperature that depends on gate-source voltage, wherein the tunnelling currents ranges from femto Amperes (fA) to pico Amperes (pA).

### Claim 13 (depends on 6)

The PTAT voltage generating circuit of claim 6, wherein the plurality of PMOS transistors are accumulation-mode gate-leakage transistors.