# US 2023/0267084 A1 · Tracing for High Bandwidth Masters in SoC

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- Number: US 2023/0267084 A1
- Document ID: US20230267084A1
- Status: Published application
- Kind: A1
- Application number: 17/677,638
- Filed: 2022-02-22
- Published: 2023-08-24
- Earliest claimed: 2022-02-22
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Mihir Narendra MODY, JR.; Ankur ANKUR; Vivek Vilas DHANDE; Kedar Satish CHITNIS; Niraj NANDAN; Brijesh JADAV; Shyam JAGANNATHAN; Prithvi Shankar YEYYADI ANANTHA; Santhanakrishnan Narayanan NARAYANAN
- Web page: https://patentgrep.com/patent/US20230267084A1

## CPC

- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 13/1673: {using buffers}
- G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus}
- G06F 15/7807: {System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A system-on-chip (SoC) in which trace data is managed includes a first memory device, a first interface to couple the first memory to a second memory external to the system-on-chip, and a first processing resource coupled to the first interface and the first memory device. The first processing resource includes a data buffer and a first direct access memory (DMA) controller. The first DMA controller transmits data from the data buffer to the first interface over a first channel, and transmits the data from the data buffer with associated trace information for the data to the first memory device over a second channel.

## Claims

### Claim 1

A system-on-chip comprising:
a first memory device;
a first interface configured to couple to a second memory device external to the system-on-chip; and
a first processing resource communicably coupled to the first interface and the first memory device, the first processing resource comprising:
a data buffer; and
a first direct memory access (DMA) controller configured to:
transmit data from the data buffer to the first interface over a first channel, and
transmit the data from the data buffer with associated trace information for the data to the first memory device over a second channel.

### Claim 2 (depends on 1)

The system-on-chip of claim 1, further comprising a system data bus, wherein the first channel and the second channel transfers are carried over the system data bus.

### Claim 3 (depends on 1)

The system-on-chip of claim 1, further comprising:
a second interface; and
a second DMA controller communicably coupled to the first processing resource, and configured to:
transmit the data with the associated trace information from the first memory device to the second interface.

### Claim 4 (depends on 3)

The system-on-chip of claim 3, wherein the second interface comprises at least one selected from a group consisting of CSI2 TX interface, a PCIE interface and Display.

### Claim 5 (depends on 3)

The system-on-chip of claim 3, further comprising an event bus communicably coupled to the first processing resource and the second DMA controller,
wherein the second DMA controller is configured to transmit the data with the associated trace information from the first memory device to the second interface in accordance with a first signal received over the event bus indicating the data from the data buffer with the associated trace information has been transmitted to the first memory device.

### Claim 6 (depends on 5)

The system-on-chip of claim 5, wherein the first processing resource further comprises a scheduler, and wherein the scheduler is configured to:
receive a second signal from the event bus indicating that the transmission by the second DMA controller is complete for a particular data set;
receive a third signal from the event bus indicating that the transmission by the first DMA controller is complete for the particular data set; and
in accordance with receiving the second signal and the third signal, cause the particular set of data to be removed from the data buffer.

### Claim 7 (depends on 5)

The system-on-chip of claim 5, further comprising:
a second processing resource communicably coupled to the first processing resource across the event bus, the second processing resource comprising:
a second data buffer; and
a third DMA controller configured to:
transmit data from the second memory device external to the system-on-chip to; and
cause a fourth signal to be transmitted across the event bus to the first processing resource indicating a data transfer rate by the second processing resource,
wherein the first processing resource is further configured to modify a production rate in accordance with the fourth signal.

### Claim 8 (depends on 7)

The system-on-chip of claim 7, further comprising:
a third processing resource having a lower throughput than the first processing resource and the second processing resource; and
a trace bus,
wherein additional data from the third processing resource is transmitted to a trace buffer via the trace bus.

### Claim 9

A system, comprising:
a system-on-chip comprising:
a first hardware accelerator (HWA) comprising:
a first buffer;
a first scheduler communicably coupled to the first buffer; and
a first direct memory access (DMA) controller;
a system data bus;
an event bus;
a first memory device coupled to the first HWA via the system data bus;
a second DMA controller coupled to the first HWA via the event bus;
a first interface coupled to the second DMA controller via the system data bus; and
a second interface coupled to the first HWA.

### Claim 10 (depends on 9)

The system of claim 9, wherein the first DMA controller is configured to transmit data from the first buffer to the second interface and to the first memory device, and wherein the second DMA controller is configured to transmit data from the first memory device to the first interface.

### Claim 11 (depends on 10)

The system of claim 10, wherein the second DMA controller is configured to transmit a first data set from the first memory device to the first interface in accordance with receiving a signal via the event bus indicating the first data set is transmitted from the first buffer to the first memory device via the first DMA controller.

### Claim 12 (depends on 9)

The system of claim 9, wherein the first interface comprises at least one selected from a group consisting of a CSI2 TX interface, PCIE interface and/or Display interface.

### Claim 13 (depends on 9)

The system of claim 9, wherein the second interface comprises external DRAM memory.

### Claim 14 (depends on 9)

The system of claim 9, wherein the system-on-chip further comprises:
a second HWA comprising:
a second buffer;
a second scheduler; and
a third DMA controller,
wherein the second DMA controller is communicably coupled to the second HWA over the event bus and further configured to transmit data from the second buffer of the second HWA to the first memory device.

### Claim 15 (depends on 14)

The system of claim 14, wherein the first HWA is configured to modify a processing rate based on a signal received via the event bus from the second HWA.

### Claim 16

A method, comprising:
transmitting, by a first direct memory access (DMA) controller, a first data set from a buffer of a processing resource to a first interface and a second data set to a first memory device over a system data bus, wherein the second data set comprises the first data set and trace data for the first data set;
transmitting, by the first DMA controller, a first signal to a second DMA controller over an event bus, wherein the first signal indicates completion of the transmission of the first data set to the first interface;
transmitting, by the first DMA controller, a second signal to a scheduler for the buffer over the event bus, wherein the second signal indicates completion of the transmission of the second data set to the first memory device; and
in response to the second signal:
transmitting, by the second DMA, the second data set from the first memory device to a second interface over the system data bus; and
transmitting, by the second DMA, a third signal to the scheduler for the buffer over the event bus, wherein the third signal indicates completion of the transmission of the second data set to the second interface.

### Claim 17

The method of 16, further comprising, in response to receiving the first signal and the third signal, clearing, by the scheduler, the first data set from the buffer.

### Claim 18 (depends on 16)

The method of claim 16, wherein the first DMA controller transmits the first data set over a first channel of the system data bus, and the first DMA controller transmits the second data set over a second channel of the system data bus.

### Claim 19 (depends on 16)

The method of claim 16, further comprising generating the second data set by:
appending a header to the first data set, wherein the header comprises identifying information for the buffer.

### Claim 20 (depends on 16)

The method of claim 16, further comprising:
in accordance with the second DMA controller transmitting the second data set from the first memory device, transmitting a fourth signal via the event bus to the scheduler,
wherein the scheduler causes the first DMA controller to transmit a third data set from the buffer in response to the fourth signal.

### Claim 21 (depends on 16)

The method of claim 16, further comprising:
receiving, by the processing resource, a fifth signal indicating a transmission rate of a second processing resource; and
modifying a processing rate of the first processing resource in response to the received fifth signal.