Chip reliability test assembly
AssigneeLuxsentek Microelectronics Corp.
InventorsCHAO-YANG HSIAO, SHENG-CHENG LEE, WEN-SHENG LIN, CHIH-WEI LIN, CHEN-HUA HSI, YUEH-HUNG HO
Life of this patent
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Abstract
The present invention proposes a chip reliability test assembly, which comprises a motherboard and a daughter board. The motherboard is used to support the chips during an aging acceleration process at high temperature. The daughter board is used to measure the electricity of chip after the aging acceleration process. Each chip holder is removable off the motherboard. The daughter board does not go through the aging acceleration process and can be reusable.
Claims10
A chip reliability test assembly, comprising:
- a motherboard used for an aging process, wherein the motherboard has a plurality of test areas, each test area includes a plurality of independent chip holders and each chip holder is used to carry a chip;
- and
- a daughter board, corresponding to the test area, used to electrically connect to the test area to perform a test process.
A chip reliability test assembly, comprising:
- a motherboard used for an aging process, wherein the motherboard has a plurality of independent chip holders, each chip holder is used to carry a chip and the chip holder can be spilled off;
- and
- a daughter board used to perform a test process, wherein the daughter board can be electrically connected to all or part of the chips on the motherboard.
A method for testing chip reliability, comprising:
- locking a motherboard in a baking box for an aging process, wherein the motherboard has a plurality of independent removable chip holders and each chip holder is used to carry a chip;
- performing an aging acceleration on the motherboard in the baking box;
- and
- combining a daughter board with the motherboard to verify a plurality of the chips at the same time.
Dependencies are inferred from the claim text.