FPGA-Based Parallel Equalization Method

Abstract

A field programmable gate array (FPGA)-based parallel equalization method is provided. The method implements efficient equalization of communication data by means of a parallel pipeline filter structure and through a least mean square (LMS) algorithm capable of dynamically adjusting a step. Firstly, a tap coefficient of an equalization filter is calculated through the LMS algorithm capable of dynamically adjusting an iteration factor. Secondly, the efficiency of FPGA data processing is improved through a multistage pipeline and a multi-channel parallel data processing. According to the present disclosure, in each clock cycle, there are M channels of data inputted into the equalization filter in parallel, and at the same time, there are also M channels of data outputted in parallel, and thus the FPGA can efficiently perform equalization processing on data acquired by a high-speed analog-to-digital converter (ADC) through the parallel pipeline method.

Dependencies are inferred from the claim text.