Semi-Additive Process for Printed Circuit Boards

A process for forming a multi-layer circuit board having an inner core and one or more pairs of outer layers, the process comprising:

• forming said inner core on a catalytic dielectric, the catalytic dielectric having catalytic particles which are exposed when the catalytic dielectric is drilled, the catalytic dielectric having a thin top foil applied to the top surface of the dielectric and a thin bottom foil applied to a bottom surface opposite the top surface, the thin bottom foil overlaid with a removable backing foil which is thicker than the thin bottom foil;
• laser drilling at least one via through the thin top foil and the catalytic dielectric to the thin bottom foil without penetrating the thin bottom foil, removing the removable backing foil, and optionally drilling at least one through hole extending through the top foil, the catalytic dielectric and the thin bottom foil,
• said laser drilled at least one via and optional thru holes thereby exposing catalytic particles on drilled surfaces of the catalytic dielectric;
• electroless plating the exposed catalytic particles, said thin top copper foil, and said thin bottom copper foil;
• applying patterned resist to create exposed copper areas and concealed copper areas of the thin top copper foil and thin bottom copper foil;
• electroplating said exposed copper areas;
• tin plating said exposed copper areas;
• stripping said patterned resist;
• quick etching the inner core until the previously concealed copper areas are etched free of copper;
• thereby forming the inner core having a top surface and a bottom surface;
• said outer layer pairs formed by applying a dielectric layer to the top surface and a dielectric layer to the bottom surface of the inner core, each dielectric layer also having a thin outer surface foil, for each applied dielectric layer:
• laser drilling at least one via and one or more optional thru holes through the top surface dielectric layer or bottom surface dielectric layer to an underlying copper layer;
• the laser drilled holes having exposed catalytic particles;
• electroless plating the exposed thin copper foil and exposed catalytic particles;
• applying patterned resist to at least one said thin outer surface foil;
• electroplating the exposed surfaces;
• plating tin onto the electroplated areas;
• stripping the patterned resist;
• quick etching the exposed copper.

A process for forming a multi-layer circuit board having an inner core and one or more pairs of outer layers, the process comprising:

• forming said inner core on an inner core catalytic dielectric, the inner core catalytic dielectric containing catalytic particles which are exposed when the catalytic dielectric is drilled, the catalytic dielectric also having a thin top foil applied to a top surface of the inner core dielectric and a thin bottom foil applied to a bottom surface opposite the inner core dielectric top surface, the thin bottom foil overlaid with a removable backing foil which is thicker than the thin bottom foil:
• laser drilling at least one via through the thin top foil, the dielectric, the at least one via reaching the thin bottom foil without penetrating the thin bottom foil;
• removing the removable backing foil;
• optionally drilling at least one through hole extending through the top foil, the dielectric and the thin bottom foil;
• said laser drilled via and optional drilled thru hole having inner surfaces with exposed catalytic particles from drilling;
• electroless plating the exposed catalytic particles, said thin top copper foil, and said thin bottom copper foil;
• applying patterned resist to create exposed copper areas and concealed copper areas of the thin top copper foil and thin bottom copper foil;
• electroplating said exposed copper areas;
• tin plating said exposed copper areas;
• stripping said patterned resist;
• quick etching the inner core until the previously concealed copper areas are etched free of copper;
• thereby forming the inner core having a top surface and a bottom surface;
• said outer layer pairs formed by applying a dielectric layer to the top surface and the bottom surface of the inner core, each dielectric layer also having a thin outer surface foil, and for each outer layer pair:
• laser drilling at least one via and one or more optional thru holes through the outer layer pair dielectric layer to an underlying copper layer;
• the laser drilled holes having exposed catalytic particles;
• electroless plating the exposed thin copper foil and exposed catalytic particles;
• applying patterned resist to at least one surface;
• electroplating the exposed surfaces;
• plating tin onto the electroplated areas;
• stripping the patterned resist;
• quick etching the exposed copper.