Parity cache for raid reliability, accessibility, and serviceability of a memory device
AssigneeMicron Technology, Inc.
InventorsPatrick Estep, Steve Pawlowski, Emanuele Confalonieri, Nicola Del Gatto, Paolo Amato
Life of this patent
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Abstract
There are provided methods and systems for improving RAS features of a memory device. For example, there is provided a system that includes a memory and a memory side cache. The system further includes a processor that is configured to minimize accesses to the memory by executing certain operations. The operations can include computing a new parity based on old data, new data, and an old parity in response to data from the memory side cache being written to the memory.
Claims20
A system, comprising:
- a memory;
- a memory side cache;
- a processor configured to minimize access to the memory by executing operations including:
- in response to data from the memory side cache being written to the memory, computing a new parity using old data, new data, and an old parity.
A method for use by a memory controller of a memory, the method comprising:
- determining whether data from a memory side cache has been written to the memory;
- and
- in response to the data having been written in the memory, computing a new parity using old data, new data, and an old parity.
Dependencies are inferred from the claim text.