Truncated array for performing division

A fixed logic circuit for performing division of an input x by a divisor selectable from a plurality of divisors, where x is an m-bit integer, the circuit comprising:

• an input configured to receive x and an indication of a selected divisor from the plurality of divisors;
• a stored plurality of multipliers corresponding to normalised versions of the plurality of divisors;
• a truncated summation array arranged to multiply the input x by any one of the plurality of multipliers, where the number of rows of the truncated array is fewer than m+[log2m]−1;
• logic configured to retrieve a multiplier from the stored plurality of multipliers based on the indication of the selected divisor and cause the truncated summation array to multiply the input x by the retrieved multiplier so as to form a first result;
• at least one stored corrective constant;
• an adder arranged to add the corrective constant to the first result so as to form a second result;
• and
• an output configured to output the second result.

A non-transitory computer readable storage medium having stored thereon computer readable code comprising a hardware dataset representation of a fixed logic circuit for performing division of an input x by a divisor selectable from a plurality of divisors, where x is an m-bit integer, the hardware dataset representation derived by:

• normalising each of the plurality of divisors to form a plurality of multipliers;
• forming a summation array arranged to multiply the input x by any one of the plurality of multipliers;
• truncating the summation array by discarding all columns less significant than the kth column of the summation array below the position of a binary point, where k=[log2m];
• determining a corrective constant in dependence on the maximum sum of the partial products discarded from the summation array for at least one of the multipliers;
• and
• generating a hardware representation of a fixed logic circuit implementing the truncated summation array including the corrective constant;
• whereby the computer readable code, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying the fixed logic circuit.