Interconnect line structures with metal chalcogenide cap materials
AssigneeIntel Corporation
InventorsCarl H. Naylor, Christopher Jezewski
Life of this patent
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Abstract
Integrated circuit interconnect structures including an interconnect line metallization feature subjected to one or more chalcogenation techniques to form a cap may reduce line resistance. A top portion of a bulk line material may be advantageously crystallized into a metal chalcogenide cap with exceptionally large crystal structure. Accordingly, chalcogenation of a top portion of a bulk material can lower scattering resistance of an interconnect line relative to alternatives where the bulk material is capped with an alternative material, such as an amorphous dielectric or a fine grained metallic or graphitic material.
Claims20
An integrated circuit (IC) interconnect structure, comprising:
- a via metallization within a dielectric material;
- and
- a line metallization over, and coupled to, the via metallization, wherein the line metallization comprises:
- a bulk material comprising a metal;
- a liner material between a bottom of the bulk material and the dielectric material;
- and
- a cap material over the bulk material, wherein the cap material comprises the metal and a chalcogen.
A computer platform comprising:
- a power supply;
- and
- an integrated circuit (IC) coupled to the power supply, wherein the IC comprises:
- a device layer comprising a plurality of transistors comprising one or more semiconductor materials;
- and
- a plurality of interconnect levels, the interconnect levels further comprising:
- a first line metallization;
- a dielectric material over the first line metallization;
- a via metallization through the dielectric material, and coupled to the first line metallization;
- and
- a second line metallization over, and coupled to, the first line metallization through the via metallization, wherein the second line metallization comprises:
- a bulk material comprising a metal;
- a liner material between a bottom of the bulk material and the dielectric material;
- and
- a cap material over the bulk material, wherein the cap material comprises the metal and a chalcogen.
A method of fabricating an integrated circuit (IC) interconnect structure, the method comprising:
- forming a trench in a dielectric material;
- depositing a liner material on a surface of the dielectric material;
- depositing a bulk material within the trench;
- planarizing the bulk material with a surface of the dielectric material;
- and
- reacting a top portion of bulk material with a chalcogen.
Dependencies are inferred from the claim text.