US 2023/0189533 A1 · SELF-ALIGNED MULTILAYER SPACER MATRIX FOR HIGH-DENSITY TRANSISTOR ARRAYS AND METHODS FOR FORMING THE SAME

Abstract

A two-dimensional array of discrete dielectric template structures is formed over a substrate. A first dielectric spacer matrix may be formed in lower portions of the trenches between the discrete dielectric template structures. A second dielectric spacer matrix layer may be formed in upper portions of the trenches. A pair of a source cavity and a drain cavity may be formed within a volume of each of the discrete dielectric template structures. A source electrode and a drain electrode may be formed in each source cavity and each drain cavity, respectively. The gate electrodes may be formed prior to, or after, formation of the two-dimensional array of discrete dielectric template structures to provide a two-dimensional array of field effect transistors that may be connected to, or may contain, memory elements.

Claims20

Dependent claims

A method of forming a semiconductor structure, comprising:

forming a two-dimensional array of discrete dielectric template structures over a substrate, wherein the discrete dielectric template structures are spaced from one another by trenches;
forming a first dielectric spacer matrix layer by depositing a first dielectric spacer material in lower portions of the trenches;
forming a second dielectric spacer matrix layer by depositing a second dielectric spacer material in upper portions of the trenches;
forming a pair of a source cavity and a drain cavity within a volume of each of the discrete dielectric template structures;
forming a source electrode and a drain electrode in each source cavity and each drain cavity, respectively;
and
forming gate electrodes prior to, or after, formation of the two-dimensional array of discrete dielectric template structures, whereby a two-dimensional array of field effect transistors is formed.

4 more elements

A semiconductor structure comprising:

a two-dimensional array of source-spacer-drain combinations located over a substrate and laterally spaced apart from one another by a composite dielectric matrix, wherein each source-spacer-drain combination selected from the two-dimensional array of source-spacer-drain combinations comprises an inter-electrode dielectric spacer in contact with a source electrode and a drain electrode, and wherein the composite dielectric matrix comprises a first dielectric spacer matrix layer comprising a first dielectric spacer material and a second dielectric spacer matrix layer comprising a second dielectric spacer material and overlying the first dielectric spacer matrix layer;
a two-dimensional array of active layers overlying, or underlying, the two-dimensional array of source-spacer-drain combinations;
gate electrodes that are spaced from the two-dimensional array of active layers by a gate dielectric layer;
and
a two-dimensional array of memory structures, wherein each memory structure within the two-dimensional array of memory structures is electrically connected to a respective source electrode within the two-dimensional array of source-spacer-drain combinations.

2 more elements

A semiconductor structure comprising:

a two-dimensional array of source-spacer-drain combinations located over a substrate and laterally spaced apart from one another by a composite dielectric matrix, wherein each source-spacer-drain combination selected from the two-dimensional array of source-spacer-drain combinations comprises an inter-electrode dielectric spacer in contact with a source electrode and a drain electrode, and wherein the composite dielectric matrix comprises a first dielectric spacer matrix layer comprising a first dielectric spacer material and a second dielectric spacer matrix layer comprising a second dielectric spacer material and overlying the first dielectric spacer matrix layer;
a two-dimensional array of active layers overlying, or underlying, the two-dimensional array of source-spacer-drain combinations;
and
a two-dimensional array of layer stacks, wherein each of the layer stacks comprises a charge storage element, a blocking dielectric layer, and a gate electrode, and is spaced from a respective active layer within the two-dimensional array of active layers by a tunneling dielectric layer.

1 more element

Dependencies are inferred from the claim text.

Self-aligned multilayer spacer matrix for high-density transistor arrays and methods for forming the same

Life of this patent

Self-aligned multilayer spacer matrix for high-density transistor arrays and methods for forming the same

Life of this patent

Abstract

Claims20